AT90S4414/8515
56
.
n: 7,6…0, pin number.
Port A Schematics
Note that all port pins are synchronized. The synchronization latch is however, not shown in the figure.
Figure 45. Port A Schematic Diagrams (Pins PA0 - PA7)
Table 20. DDAn Effects on Port A Pins
DDAn PORTAn I/O Pull up Comment
0 0 Input No Tri-state (Hi-Z)
0 1 Input Yes PAn will source current if ext. pulled low.
1 0 Output No Push-Pull Zero Output
1 1 Output No Push-Pull One Output
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