Atmel AT90S8515-8PI - External Data Memory Timing; 1 Cycle Wait State Timing

AT90S4414/8515
85
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 40. External Data Memory Characteristics, 2.7 - 4.0 Volts, No Wait State
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 4.0 MHz
1t
LHLL
ALE Pulse Width 70.0 0.5t
CLCL
-55.0
(1)
ns
2t
AVLL
Address Valid A to ALE Low 60.0 0.5t
CLCL
-65.0
(1)
ns
3a t
LLAX_ST
Address Hold After ALE Low,
ST/STD/STS Instructions
130.0 0.5t
CLCL
+5.0
(2)
ns
3b t
LLAX_LD
Address Hold after ALE Low,
LD/LDD/LDS Instructions
15.0 15.0
ns
4t
AVLLC
Address Valid C to ALE Low 60.0 0.5t
CLCL
-65.0
(1)
ns
5t
AVRL
Address Valid to RD Low 200.0 1.0t
CLCL
-50.0 ns
6t
AVWL
Address Valid to WR Low 325.0 1.5t
CLCL
-50.0
(1)
ns
7t
LLWL
ALE Low to WR Low 230.0 270.0 1.0t
CLCL
-20.0 1.0t
CLCL
+20.0 ns
8t
LLRL
ALE Low to RD Low 105.0 145.0 0.5t
CLCL
-20.0
(2)
0.5t
CLCL
+20.0
(2)
ns
9t
DVRH
Data Setup to RD High 95.0 95.0 ns
10 t
RLDV
Read Low to Data Valid 170.0 1.0t
CLCL
-80.0 ns
11 t
RHDX
Data Hold After RD High 0.0 0.0 ns
12 t
RLRH
RD Pulse Width 230.0 1.0t
CLCL
-20.0 ns
13 t
DVWL
Data Setup to WR Low 70.0 0.5t
CLCL
-55.0
(1)
ns
14 t
WHDX
Data Hold After WR High 0.0 0.0 ns
15 t
DVWH
Data Valid to WR High 210.0 1.0t
CLCL
-40.0 ns
16 t
WLWH
WR Pulse Width 105.0 0.5t
CLCL
-20.0
(2)
ns
Table 41. External Data Memory Characteristics, 2.7 - 4.0 Volts, 1 Cycle Wait State
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 4.0 MHz
10 t
RLDV
Read Low to Data Valid 420.00 2.0t
CLCL
-80.0 ns
12 t
RLRH
RD Pulse Width 480.0 2.0t
CLCL
-20.0 ns
15 t
DVWH
Data Valid to WR High 460.0 2.0t
CLCL
-40.0 ns
16 t
WLWH
WR Pulse Width 355.0 1.5t
CLCL
-20.0
(2)
ns