Baumer_PowerlinkV1-01_MA_EN.docx 8/19 www.baumer.com
19.07.2013
5 Technical specifications
5.1 Powerlink specifications
The bus cover complies with following specifications:
5.2 Ethernet specifications
Delay internal Hub (Daisy Chain)
2 outputs: M12 D-coded (Auto-Negation)
5.3 Timing behavior
The following table describes the delay and jitter between the Start of Cycle (SoC) and acquisition of a new
position value.
BMSx (ST):
BMMx (MT):
GXAMx (ST):
GXMMx (MT):
GBAMx (ST):
GBMMx (MT):
11,34µs
13,84µs
5,00µs
5,00µs
7,20µs
7,20µs
+- 7,6µs (=7,5µs +/- 68ns)
+- 10,1µs (= 10µs +/- 68ns)
+- 0,6µs (= 0,54µs +/- 68ns)
+- 0,6µs (= 0,54µs +/- 68ns)
+-1,3µs (= 1,2µs +/- 68ns)
+-1,3µs (= 1,2µs +/- 68ns)
5.4 Physical resolution for each product
The following table describes the non-scaled physical resolution dependent on the used basic encoder.