Beck IPC@CHIP - SC12 User Manual

IPC@CHIP - SC12
Hardware Manual v1.1 [05.11.2002]
©BECK IPC GmbH page 12 of 28
4.9 I
2
C-Bus
The IPC@CHIP family microcontroller handles up to 127 external slaves. It is always master. Slave
mode is not implemented.
I²C is implemented by software emulation. Maximum Frequency is about 30 kHz without longer breaks
by interrupt. External pullups are necessary.
Pin Name Type Function
I2C_SCL O
I
2
C-Bus Clock (output)
This pin provides clock to an external I
2
C slave by default. Any other PIO pin
may be assigned for use as I
2
C_SCL signal by software.
I2C_SDA I/O
I
2
C-Bus Data in/out (input/output)
This pin acts either as data input or data output as defined by the I
2
C protocol
convention. Any other PIO pin may be assigned for use as I
2
C_DAT signal by
software.
4.10 Reset, Power Fail Generator
Note that RESET# pin shares 4 functions: RESET and NMI as described here, as well as network link
state and network traffic as described in the corresponding chapters.
This is a voltage-multiplexed pin that internally sinks current only in case of internally generated reset
or NMI condition. All peripheral logic asserted to this pin must be open-collector to prevent the internal
logic from sinking too high current. It is provided with 1kOhm Pullup.
Pin Name Type Function
RESET# I/O
Reset (input/level-sensitive)
If voltage on this pin goes below 0.8V the microcontroller will perform a reset.
In that case the microcontroller immediately terminates its present activity,
clears it’s internal logic, and transfers CPU control to the reset address,
FFFF0h.
If Vcc goes down below 4.65V or the internal watchdog is triggered this pin will
be driven to GND internally.
NMI I
Nonmaskable Interrupt (input, level-sensitive)
If voltage on this pin goes down below 1.5V it indicates to the microcontroller
that an interrupt request has occurred. The NMI signal is the highest priority
hardware interrupt and, unlike the INT6–INT0 pins, cannot be masked. The
microcontroller always transfers program execution to the location specified by
the nonmaskable interrupt vector in the microcontroller interrupt vector table
when NMI is asserted.
Although NMI is the highest priority interrupt source, it does not participate in
the priority resolution process of the maskable interrupts.
There is no bit associated with NMI in the interrupt in-service or interrupt
request registers. This means that a new NMI request can interrupt an
executing NMI interrupt service routine. As with all hardware interrupts, the IF
(interrupt flag) is cleared when the processor takes the interrupt, disabling the
maskable interrupt sources. However, if maskable interrupts are re-enabled by
software in the NMI interrupt service routine, via the STI instruction for
example, the fact that an NMI is currently in service does not have any effect
on the priority resolution of maskable interrupt requests. For this reason, it is
strongly advised that the interrupt service routine for NMI should not enable the
maskable interrupts. An NMI transition from Low to High is latched and
synchronized internally, and it initiates the interrupt at the next instruction
boundary. To guarantee that the interrupt is recognized, the NMI condition
must be asserted to the pin for at least one CLK period.

Beck IPC@CHIP - SC12 Specifications

General

Brand	Beck
Model	IPC@CHIP - SC12
Category	Microcontrollers
Language	English