Beck IPC@CHIP - SC12 User Manual

IPC@CHIP - SC12
Hardware Manual v1.1 [05.11.2002]
©BECK IPC GmbH page 9 of 28
4.3 Programmable Chip Selects
Pin Name Type Function
PCS[0..3] O
Peripheral Chip Selects (output)
These pins indicate to the system that an I/O memory access is in
progress to the corresponding region of the peripheral memory.
PCS0–PCS3 are three-stated and held resistively High during a bus
hold condition. In addition, PCS0–PCS3 each have a weak internal
pullup resistor that is active during reset. The PCS outputs assert with
the multiplexed AD address bus. Note also that each peripheral chip
select asserts over a 256-byte address range. PCS0–PCS3 have
extended wait state options, active for at least 800ns.
PCS[5..6] O
Peripheral Chip Selects (output)
These pins indicate to the system that an I/O memory access is in
progress to the corresponding region of the peripheral memory.
PCS5–PCS6 are three-stated and held resistively High during a bus
hold condition. In addition, PCS5–PCS6 each have a weak internal
pullup resistor that is active during reset. The PCS outputs assert with
the multiplexed AD address bus. Note also that each peripheral chip
select asserts over a 256-byte address range. PCS5–PCS6 also have
wait state, active for at least 150ns.
4.4 Interrupts
Pin Name Type Function
INT[0,2-6] I
Maskable Interrupt Request (input)
These pins indicate to the microcontroller that an interrupt request has
occurred. If the INT pin is not masked, the microcontroller transfers program
execution to the location specified by the corresponding INT vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can be edge-triggered or
level-triggered. To guarantee interrupt recognition, the requesting device
must continue asserting INT until the request is acknowledged. INT2
becomes INTA# when INT0 is configured in cascade mode. *
INTA# * O
Interrupt Acknowledge (output)
When the microcontroller interrupt control unit is operating in cascade
mode, this pin indicates to the system that the microcontroller needs an
interrupt type to process the interrupt request on INT0. The peripheral
issuing the interrupt request must provide the microcontroller with the
corresponding interrupt type.
PWD IS
Pulse Width Demodulator (input, Schmitt trigger)
If pulse width demodulation is enabled, PWD processes the signal through
a Schmitt trigger. PWD is used internally to drive TMRIN0 and INT2, and
PWD is inverted internally to drive TIMERIN1 and INT4. If INT2 and INT4
are enabled and timer 0 and timer 1 are properly configured, the pulse width
of the alternating PWD signal can be calculated by comparing the values in
timer 0 and timer 1.
In PWD mode, the signals TMRIN0, TMRIN1 and INT4 can be used as
PIOs. If they are not used as PIOs, they are ignored internally.
* currently not supported by software

Beck IPC@CHIP - SC12 Specifications

General

Brand	Beck
Model	IPC@CHIP - SC12
Category	Microcontrollers
Language	English