Beck IPC@CHIP - SC12 - Ac-Characteristics; Read Cycle

IPC@CHIP - SC12
Hardware Manual v1.1 [05.11.2002]
©BECK IPC GmbH page 21 of 28
8.4 AC-CHARACTERISTICS
8.4.1 Read Cycle
No. Symbol Description Min Max Unit
General Timing Requirements
1 t
RLDV
Read Valid to Data Valid – PCS0#..PCS3# Active 820 ns
1 t
RLDV
Read Valid to Data Valid – PCS5#, PCS6# Active 220 ns
General Timing Responses
10 t
LHLL
ALE Width 40 ns
12 t
AVLL
AD Address Valid to ALE Low 23 ns
13 t
LLAX
AD Address Hold from ALE Inactive 23 ns
17 t
CXCSX
PCSx# Hold from Read Inactive 23 ns
23 t
LHAV
ALE High to Address Valid 20 ns
99 t
PLAL
PCSx# Active to ALE Inactive 15 28 ns
Read Cycle Timing Responses
24 t
AZRL
AD Address Float to Read Active 0 ns
26 t
RLRH
Read Pulse Width – PCS0#..PCS3# Active 835 ns
26 t
RLRH
Read Pulse Width – PCS5#, PCS6# Active 235 ns
28 t
RHLH
Read Inactive to ALE High (a) 22 ns
29 t
RHAV
Read Inactive to AD Address Active (a) 40 ns
59 t
RHDX
Read Inactive to Data Hold on AD Bus 0 ns
(a) This parameter applies to the WR# signal
Addres
s
Data
17
26
24
28
12
99
10
29
1323 1 59
AD0..AD7
ALE
RD#
PCSx#
*) the falling edge of PCS1# is 50nS delayed internaly