IPC@CHIP - SC12
Hardware Manual v1.1 [05.11.2002]
©BECK IPC GmbH page 19 of 28
7.2 System interrupts
Number of Interrupt
Source Sensitivity
0 = INT0 (external) Edge / Level
1 = Network controller (internal)
2 = INT2 (external) Edge / Level
3 = INT3 (external) Edge / Level
4 = INT4 (external) Edge / Level
5 = INT5 (external) Edge
6 = INT6 (external) Edge
7 = Reserved
8 = Timer0 (internal)
9 = Timer1 (internal)
10 = Timer 1ms (internal) (*)
11 = Serial port 0 (internal) (*)
12 = Serial port 1 (internal) (*)
13 = Terminal count DMA channel 0 (internal) (*)
14 = Terminal count DMA channel 1 (internal) (*)
15 = NMI (internal/external)
(*) = Currently not supported
Since an interrupt occurs all interrupts are disabled until the interrupts are released by setting IF Flag
in interrupt service routine. Interrupts of the same source are masked until the corresponding Bit in
interrupt service register is cleared.
Level sensitiv interrupts are caused by high level, edge sensitiv interrupts by the rising edge.
7.3 Watchdog
The build in watchdog prevent the SC12 to lead to an unexpected fail mode in software and hardware.
The watchdog timeout period is about 838 ms. The mode can set to trigger the watchdog by user
programm or by the BIOS (default). In BIOS mode, the BIOS performs the watchdog strobing provided
that the system's timer interrupt is allowed to execute. Beware that excessive interrupt masking
periods can lead to system resets.
To Next Page
Loading...
Need help?
General
