IPC@CHIP - SC12
Hardware Manual v1.1 [05.11.2002]
©BECK IPC GmbH page 3 of 28
1. BASIC SPECIFICATIONS
@CHIP CPU RAM FLASH Ethernet
SC12 80186 20MHz 512 Kbytes 512 Kbytes 10Base-T
IPC@CHIP® family 80186- and 80188-compatible microcontroller with up to 512KB-RAM, 512KB
Flash and Ethernet on Chip
- Lower system cost with higher performance
High performance
- 20-MHz operating frequency
- Zero-wait-state operation at 20 MHz (RAM)
- 1-Mbyte internal memory space
- 6 x 256-byte I/O space
- Low-power CMOS process with single 5V power supply
Enhanced integrated peripherals
- Up to 14 programmable I/O (PIO) pins
- Two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers,
Serial port hardware handshaking with CTS and RTS selectable for each port
Independent serial port baud rate generators
DMA to and from the serial ports
- Ethernet controller for IEEE 802.3, 10Base-T,
Integrated 10Base-T transceiver (SC12 only)
Auto-Polarity detection and correction
Loopback capability for diagnostics
Receiver and collision squelch circuit to reduce noise
Built-in pre-distortion resistors for 10Base-T application
- Watchdog timer
- Pulse-width demodulation option
Familiar 80C186 peripherals
- Two independent DMA channels
- Programmable interrupt controller with up to six external interrupts
- Three programmable 16-bit timers, the 2 input timers are interrupt capable
- Programmable memory and peripheral chip-select logic
Software-compatible with the 80C186 and 80C188 microcontrollers with widely available native
development tools, applications, and system software
Available in the following packages:
- 32-pin, plastic pack (DIL32)
The @CHIP SC12 microcontrollers are part of the Beck IPC@CHIP® family of System on Chip
microcontrollers and microprocessors based on the x86 architecture. The IPC@CHIP family
microcontroller is the ideal solution for new designs requiring Ethernet TCP/IP communication over
twisted pair and/or through the serial port. The compatibility with the 80C186/188 family makes it also
an ideal upgrade for systems based upon this processor range but requiring increased performance,
serial communications, Ethernet communications, a direct bus inter-face, or more than 64K of
memory.
The IPC@CHIP family microcontrollers integrates up to 512Kbyte DRAM with increased
performance and up to 512Kbyte FLASH reducing memory subsystem costs.
The minimum endurance of the flash memory is at 10,000 cycles (depend on environmental stress
e.g. temperature).