Brother HL-2030 - Main PCB Block Diagram

CHAPTER 3 THEORY OF OPERATION
Confidential
3-2
1.2 Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB. (HL-2030/2040/2070N)
Reset Circuit
Program + Font ROM
HL-2030/2040: 1MB
HL-2070N: 8MB
RAM
HL-2030/2040: 8MB
HL-2070N: 16MB
EEPROM
HL-2030/2040: 512 x 8 bit
HL-2070N: 4096 x 8 bit
CPU Core (SPARClite)
HL-2030/2040: 96.0MHz
HL-2070N: 133.0MHz
A S I C
Oscillator
HL-2030/2040: 48.0MHz
HL-2070N: 66.6MHz
Address Decoder
DRAM Control
Timer
FIFO
CDCC Parallel I/O
(E
xternal Gate Array)
Soft Support
EEPROM I/O
Engine Control I/O
INTBUS
To PC
USB I/O
To PC
Network Program
(HL-2070N only)
Network Controller
To PC
or Hub
(HL-2070N only)
Oscillator 12MHz
Oscillator 25MHz
(HL-2070N only)
Fig. 3-2