%
%
40
&" #"! !$! #
(98/12/10)
14h -- Reserved
15h RECR Receive Error Counter Register
16h SRR Silicon Revision Register
17h PCR PCS Sub-Layer Configuration Register
18h LBREMR Loopback,Bypass,Receiver Error Mask Reg.
19h PAR Physical Address Register
1Ah -- Reserved
1Bh 10BTSR 10BASE-T Status Register
1Ch 10BTCR 10BASE-T Configuration Register
1Dh–1Fh -- Reserved
Differences between DP83840 and 83840A
00h BMCR 6 Reserved Management Frame
Preamble Suppression
indicator selectable
03h PHYIDR2 3:0 set to 0000 set to 0001
05h ANLPAR 5 Does not reflect Link
Partner 10BASE-T AbilĆ
ity after parallel
detection
Reflects Link Partner
10BASE-T Ability after
parallel detection
05h ANLPAR 7 Does not reflect Link
Partner 100BASE-T
Ability after parallel
detection
Reflects Link Partner
100BASE-T Ability after
parallel detection
16h SRR 15:0 set to 0x0000 set to 0x0001
17h PCR 14 Stream Cipher time-
out timer is fixed
Stream Cipher time-
out timer is selectable
18h LBREMR 5 Reserved Able to disable/enable
the TD+/- outputs durĆ
ing 100BASE-T loopĆ
back
18h LBREMR 6 Reserved Control CSR behavior
during Full-duplex opĆ
eration
18h LBREMR 15 Does not control Bad
SSD code generation
Control Bad SSD code
generation
To Next Page
Loading...