Clevo N650DU Series - Power Sequence

Schematic Diagrams
Power Sequence B - 45
B.Schematic Diagrams
Power Sequence
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
N650DU PWR SEQ
450 6504000 300200 550100
[1] RTCVCC
t=29uS
[4] BATLOW_N
[2]
t=Min 9mS
[5] ACPRESENT
RTCRST#
97.9mS 599mS
[3] VDD3
[20] PCH_SYSPWROK_AND
200mS
N650DU Power On Sequence
[29] VDDQ_VT
204mS
[30] VCCST_PWRGD
204mS
[32] DDR_VTT_CNTL
204.1mS
[31] VCCSA_READY
204mS
569.9mS
PCH_SYSPWROK_EC[33]
[34] H_PWRGD
99.1mS
298.6mS 271.3mS
374.4mS
VCORE[35]
382.5mS
PLTRST_CPU_N[36]
382.6mS
PLTRST_N[37]
[24] VCCIO
201.1mS
[25] VCCIO_PWRGD
201.1mS
[28] PCH_PWROK
203.9mS
[27] VR_READY_VCORE
203.3mS
VCCSA[26]
202mS
[21] VCCST_VCCPLL
200.4mS
[22] VDDQ
521.2mS
[8] 3.3VA
[9] 1.0VA
200.9mS
[23] ALL_SYS_PWRGD
521.8mS
[10] PWR_SW#
201mS
480.8mS
354.7mS
DD_ON[11]
355.1mS
[12] 3.3V
356.3mS
[13] 5V
[14] PCH_RSMRST_N_EC
81.3mS
[15] PWR_BTN_N
81.3mS
183.2mS
[16] SUSB#
199.5mS
[17] SUSC#
199.5mS
[18] 3.3VS
200mS
518.8mS
[6] EC_SLP_SUS_N
521.3mS
[7]
VCC_3P3A_PWRGD
[19] VCCIO_EN
200mS
150 600350250 50050 450 6504003000 200 550100
N650DU Power Down Sequence 2
150 600350250 50050
t=1.9774mS
t=468.973mS
VDD5[10]
t=469.97mS
5V[11]
t=539.08mS
3.3V[12]
450 6504003000 200 550100
N650DU SUSPEND Sequence 3
150 600350250 50050
5V[10]
3.3V[11]
[12] VDD5
[1]
VDDQ_VT[2]
3.3VS
VCCIO[3]
VCORE[4]
VCCSA[5]
5VS[6]
[7] VCCST_VCCPLL
2.5V[8]
VDDQ[9]
t=308.5uS
t=2.8577mS
t=4.0432mS
t=3.2422mS
t=3.2162mS
VDDQ[1]
t=1.9mS
VDDQ_VT[2]
VCCST_VCCPLL[3]
t=1.5867mS
t=336uS
2.5V[4]
3.3VS[5]
t=2.9267mS
VCCIO[6]
t=3.2972mS
VCCSA[7]
t=3.4377mS
VCORE[8]
t=3.9185mS
5VS[9]
Title
Size Document Number Rev
Date: Sheet
of
2.0
[44] POWER SEQUENCE
Custom
44 44Thursday, Mar ch 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
2.0
[44] POWER SEQUENCE
Custom
44 44Thursday, Mar ch 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
2.0
[44] POWER SEQUENCE
Custom
44 44Thursday, Mar ch 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Sheet 44 of 44
Power Sequence