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Clevo N650DU Series - Processor Schematics

Clevo N650DU Series
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Schematic Diagrams
Processor 1/7 B - 3
B.Schematic Diagrams
Processor 1/7
Sheet 2 of 44
Processor 1/7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SKYLAKE-S Processor 1/7 ( DMI,FDI,PEG )
20 mil
VGA SIDE
CAD NOTE: PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
- typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with
- max length = 500 mils
- typical impedance = 14.5 mohms
K/B
⬠⭂ỵ
3.3V
VCCIO
GND GND GND
GND GND GND
GND GND GND
THERM_VOLT 31
DMI_RX0_P19
DMI_RX0_N19
DMI_RX1_P19
DMI_RX1_N19
DMI_RX2_P19
DMI_RX2_N19
DMI_RX3_P19
DMI_RX3_N19
DMI_TX0_P 19
DMI_TX0_N 19
DMI_TX1_P 19
DMI_TX1_N 19
DMI_TX2_P 19
DMI_TX2_N 19
DMI_TX3_P 19
DMI_TX3_N 19
3.3V12,14,15,16,18,21,22,23,24,25,26,27,32,36,37
VCCIO5,6,36
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[02] PROCESSOR 1/7
A4
244Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[02] PROCESSOR 1/7
A4
244Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[02] PROCESSOR 1/7
A4
244Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
H17
*H8_0D2_8
1
H18
*MTH8_0D2_8
2
3
4
5
M8
*M-MARK
H2
*C111D111N
1
H22
*MTH8_0D2_8
2
3
4
5
LGA1151
SKL_S_CPU
3 OF 12
REV = 1.2
U1C
3H993921-4M41-02H
PEG_RXN[2]
D5
PEG_RXP[2]
D6
PEG_RXP[3]
E5
PEG_RXN[3]
E4
PEG_RXN[4]
F5
PEG_RXP[0]
B8
PEG_RXP[13]
R5
DMI_TXN[3]
AF3
DMI_TXP[3]
AF2
DMI_TXN[2]
AE1
DMI_TXP[2]
AE2
DMI_TXP[1]
AD3
DMI_TXN[1]
AD2
DMI_TXN[0]
AC1
DMI_TXP[0]
AC2
DMI_RXP[3]
AC4
DMI_RXN[3]
AC5
DMI_RXN[2]
AB3
DMI_RXP[2]
AB4
DMI_RXP[1]
AA4
DMI_RXN[1]
AA5
DMI_RXP[0]
Y3
DMI_RXN[0]
Y4
PEG_RCOMP
L7
PEG_RXP[15]
U5
PEG_RXP[14]
T6
PEG_RXN[15]
U4
PEG_RXP[8]
K6
PEG_RXN[7]
J4
PEG_RXP[7]
J5
PEG_RXN[0]
B7
PEG_RXP[1]
C7
PEG_RXN[1]
C6
PEG_RXP[4]
F6
PEG_RXP[5]
G5
PEG_RXP[6]
H6
PEG_RXP[10]
M6
PEG_RXN[10]
M5
PEG_RXP[11]
N5
PEG_RXN[11]
N4
PEG_RXP[12]
P6
PEG_RXN[13]
R4
PEG_RXN[14]
T5
PEG_TXP[0]
A5
PEG_TXN[0]
A6
PEG_TXP[1]
B4
PEG_TXN[1]
B5
PEG_TXN[2]
C4
PEG_TXP[2]
C3
PEG_TXN[3]
D3
PEG_TXP[3]
D2
PEG_TXP[4]
E1
PEG_TXN[5]
F3
PEG_TXN[4]
E2
PEG_TXP[5]
F2
PEG_TXN[6]
G2
PEG_TXP[6]
G1
PEG_TXP[7]
H2
PEG_TXP[8]
J1
PEG_TXN[10]
L2
PEG_TXP[10]
L1
PEG_TXN[9]
K3
PEG_TXP[11]
M2
PEG_TXN[11]
M3
PEG_TXN[12]
N2
PEG_TXP[12]
N1
PEG_TXN[13]
P3
PEG_TXP[13]
P2
PEG_TXN[14]
R1
PEG_TXP[14]
R2
PEG_TXP[15]
T2
PEG_TXN[15]
T3
PEG_RXN[12]
P5
PEG_RXN[9]
L4
PEG_RXN[8]
K5
PEG_TXP[9]
K2
PEG_TXN[8]
J2
PEG_RXP[9]
L5
PEG_TXN[7]
H3
PEG_RXN[5]
G4
PEG_RXN[6]
H5
H1
*C111D111N
1
H4
*MTH8_0D2_8
2
3
4
5
1
H19
*MTH8_0D2_8
2
3
4
5
H26
*C111D111N
H13
*H6_0D4_0
H25
*C111D111N
1
H20
*MTH8_0D2_8
2
3
4
5
1
H3
*MTH8_0D2_8
2
3
4
5
1
H6
*MTH8_0D2_8
2
3
4
5
RT1
TH05-3H103FR
P/N = 6-17-10320-731
10K_1%_NTC_04
1 2
R136
10K_1%_04
H12
*H10_0D6_0
H7
*H10_0D6_0
H9
*H8_0B7_5D5_5
H14
*H8_0B7_5D5_5
H11
*H8_0B7_5D5_5
M4
*M-MARK
H15
*H6_0D3_7
H5
*H3_5D2_5
H10
*H6_0D4_0
M2
*M-MARK
R13224.9_1%_04
M6
*M-MARK
1
H8
*MTH8_0D2_8
2
3
4
5
1
H23
*MTH8_0D2_8
2
3
4
5
M5
*M-MARK
M3
*M-MARK
H16
*H8_0B7_5D5_5
H21
*H3_5D2_5
M7
*M-MARK
H24
*H3_5D2_5
M1
*M-MARK
PEG_IRCOMP_R

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