5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SKY LAKE - S (SPI,GSX,GPP)
PLATFOR M R ST BUFFER
DESIGN NOTE:
BIOS+EC ROM
SPI_* = 1.5"~6.5"
ME ROM
16Mbit
DESIGN NOTE:
Function Table
L
L
L
L
AB
L
H
HL
Y
HH
L
H
DESIGN NOTE:
ESPI FLASH SHARING MODE
0: MASTER ATTACHED FLASH SHARING
1: SLAVE ATT ACEHD FLASH SHARING
PCH HAS INT ERNAL WEAK PD
DESIGN NOTE:
JTAG ODT IS DISABLED IF LOW
PCH HAS INT ERNAL WEAK PU
DESIGN NOTE:
BOOT HALT ENABLED IF LOW
PCH HAS INT ERNAL WEAK PU
DESIGN NOTE:
CONSENT STRAP
ENABLE:LOW
(INTE RNAL WEAK PU)
PESONALITY ST RAP
ENABLE:LOW
(INTE RNAL WEAK PU)
DESIGN NOTE:
VCCIO_EN=(VDDQ_PWRGD & SUSB#)
EC DELAY 99ms(UP)
MAIN 6-04-25643-490
SECOND 6-04-02564-470
WIGIG GPIO
V3P3A_V1P8A_PCH
3.3VS
3.3V_SPI
VRTC
3.3VS
3.3V
V3P3A_V1P8A_PCH
V3P3A_V1P8A_PCH_SPI
V3P3A_V1P8A_PCH_SPI
V3P3A_V1P8A_PCH_SPI
V3P3A_V1P8A_PCH_SPI
V3P3A_V1P8A_PCH_SPI
VDD3VDD3
VDD3
VDD3
V3P3A_V1P8A_PCH_SPI
VDD316,17,19,20,23,27,29,31,32,35,36,37,38,39
3.3VS5,9,10,11,12,13,14,16,17,18,20,21,22,24,25,26,27,28,29,30,31,32,33,35,36
3.3V2,12,14,16,18,21,22,23,24,25,26,27,32,36,37
PLTRST_N_BUF 25,27,29
PLTRST_N_EC 31
VRTC16,20
PCH_DRQ1_N 27
SPI_SCLK_R31
SPI_CS0_R_N31
SPI_MISO31
SPI_MOSI31
VCCIO_EN36
SUSB#16,25,26,31,32
VCCSA_READY35
VCCIO_PWRGD33,35,36
PCH_SYSPWROK_EC31
PCH_SYSPWROK_AND 16
PCH_PWROK 10,16
VCCST_PWRGD 3
ALL_SYS_PWRGD 12,31
V3P3A_V1P8A_PCH20
3.3VA3,10,14,16,17,19,20,32
V3P3A_V1P8A_PCH_SPI20
PLTRST_PCIE_SLOTS_N 23,24,29
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[15] SKY LAKE - H (SPI,GSX,GPP)
A3
15 44Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[15] SKY LAKE - H (SPI,GSX,GPP)
A3
15 44Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[15] SKY LAKE - H (SPI,GSX,GPP)
A3
15 44Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
R304 *10mil_short
R327 *4.7K_04
U9A
74LVC08APW
1
2
3
147
R673 33_04
R219
10K_04
R292 30.1_1%_04
U9C
74LVC08APW
9
10
8
147
R353 33_04
C323
0.1u_16V_Y5V_04
R352
*10mil_short
R273 *10K_04
R319 *20K_04
R401 33_04
R326 *1K_04
R392
1K_1%_04
C221
0.1u_10V_X7R_04
R677 33_04
R164 *10K_04
R381 *10mil_short
R396
1K_1%_04
R364 33_04
R225
10K_04
R233 1K_04
R229 *10mil_short
R247
33_04
U9B
74LVC08APW
4
5
6
147
U11
GD25B64CSIGR
PCB Footprint = M-SOP8B
CE#
1
SO
2
WP#
3
VSS
4
SI
5
SCK
6
HOLD#
7
VDD
8
R402 *4.7K_04
R166 *10K_04
U9D
74LVC08APW
12
13
11
147
U24
U74AHC1G08G-AL5-R
1
2
5
4
3
R400 *4.7K_04
R678 1K_04
R165 *1K_04
R580 *10K_04
R371
*15mil_short
R240
33_04
R368
100K_04
R248 *20K_04
R277 1M_04
R235
10K_04
R641
10K_04
R395 *20K_04
R320 *20K_04
SKL_PCH_H
REV = 1.3
1 OF 12
U8A
H170 MP
INTRUDER#
BE11
GPP_H10/SML2CLK
BD34
GPP_H11/SML2DATA
AW35
GPP_H12/SML2ALERT#
BD35
GPP_H13/SML3CLK
BC35
GPP_H14/SML3DATA
BA35
GPP_H15/SML3ALERT#
BB36
GPP_H16/SML4CLK
BD39
GPP_H17/SML4DATA
BE34
GPP_H18/SML4ALERT#
BC36
GPP_B4/CPU_GP3
BD24
GPP_B3/CPU_GP2
BC23
GPP_E7/CPU_GP1
AE44
GPP_E3/CPU_GP0
AF41
GPP_G15/GSXSRESET#
R41
GPP_G14/GSXDIN
R42
GPP_G13/GSXSLOAD
R36
GPP_G12/GSXDOUT
R39
GPP_G16/GSXCLK
P43
GPP_B13/PLTRST#
BB27
GPP_D21
AG44
GPP_D22
AH43
GPP_D3
AN41
GPP_D0
AL39
SPI0_CS2#
AT31
SPI0_IO3
BD30
SPI0_IO2
BC29
SPI0_CLK
BC31
SPI0_CS0#
BD31
RSVD
AE17
RSVD
AF17
RSVD
AG14
TP5
AR19
TP4
AN17
SPI0_MOSI
BB29
SPI0_MISO
BE30
SPI0_CS1#
AW31
GPP_D1
AN36
GPP_D2
AN38
RSVD
AG15
GPP_A11/PME#
BD17
R237 *4.7K_04
SPI_CS0_N
SPI_SI
SPI_SO
SPI_SCLK
SPI_CS0_R_N
SPI_CS1_R_N
SPI_MOSI
SPI_SCLK_R
SPI_MISO
PLTRST_NPLTRST_R_N
PLTRST_N
TBT_FRC_PWR
TBCIO_PLUG_EVENT
PCH_GPP_G_13
M.2 _W IGIG_W GPIO
M.2_WIGIG_WAKE_CTRL_N
PCH_GPP_E_3
PCH_GPP_E_7
BT_RF_KILL_R_N
USB_DET_PLUG_EVENT
PCH_GPP_H_18
M.2_WIGIG_RST_R
M.2_WIGIG_WAKE_R_N
PCH_GPP_H_13
GPP_H_12
PCH_GPP_H_10
EXTTS_SNI_DRV1_PCH
SPI_WP0_N
SPI_HOLD0_N
SPI_CS0_N
SPI_SI
SPI_SO
SPI_SCLK
PME_N
M.2 _W IGIG_W GPIO
SPI_DQ2
SPI_DQ3SPI_HOLD0_N
SPI_WP0_N
SPI_CS2_N
SPI_CS0_R_N
SPI_SCLK_R
SPI_MISO
SPI_MOSI
GPP_H_12
SPI_MISO
SPI_MOSI
SPI_DQ2
SPI_DQ3
SYS_PWROK_R
TBTA_MRESET
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