Clevo N650DU Series - Processor 2;7

Schematic Diagrams
B - 4 Processor 2/7
B.Schematic Diagrams
Processor 2/7
Sheet 3 of 44
Processor 2/7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SKYLAKE-S Processor 2/7 (JTAG,CLK,CFG )
CPU_24MHZ
DESIGN NOTE:
H_TCK TERMINATION PLACE NEAR CPU WITHIN 1.1 INCH
DESIGN NOTE:
CFG[4]
1:Disabled - No Physical Display Port
attached to Embedded DisplayPort*.
No connect for disable.
0:Enabled - A Display Port device is
connected to the Embedded Display Port.
Pull-down to GND through a 1 K? ±5%
resistor to enable port.
DESIGN NOTE:
CFG[6:5]
00 = 1x8, 2x4 PCI Express* 01 = reserved
10 = 2x8 PCI Express* 11 = 1x16 PCI Express*
Recommend 1K ? ±5% pull-down resistor to GND.
PU/PD for JTAG signals
DESIGN NOTE:
CFG[7]
1 = (default) PEG train immediately following
RESET# de assertion.
0 = PEG wait BIOS for training.
CAD Note: Capacitor need to be placed
close to buffer output pin
VCCST_VCCPLL
3.3VA
VCCST_VCCPLL
3.3VS5,9,10,11,12,13,14,15,16,17,18,20,21,22,24,25,26,27,28,29,30,31,32,33,35,36
VCCST_VCCPLL6,16,33,36
3.3V2,12,14,15,16,18,21,22,23,24,25,26,27,32,36,37
PECI_HDR14,31
PCH_THERMTRIP_N14
H_PM_SYNC14
H_VIDALERT_N_VR33
H_VIDSCK_VR33
H_VIDSOUT_VR33
PCH_CPU_BCLK_DP18
PCH_CPU_BCLK_DN18
PCH_CPU_PCIBCLK_DP18
PCH_CPU_PCIBCLK_DN18
PCH_CPU_NSSC_CLK_DP18
PCH_CPU_NSSC_CLK_DN18
H_PROCHOT_N3,33,39
VCCST_PWRGD15
H_PWRGD16
PLTRST_CPU_N14
H_PM_DOWN14
H_SKTOCC_N17
H_PROCHOT_EC_N31
H_PROCHOT_N 3,33,39
3.3VA10,14,16,17,19,20,32
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[03] PROCESSOR 2/7
A4
344Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[03] PROCESSOR 2/7
A4
344Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
Title
Size Document Number Rev
Date: Sheet
of
6-71-N6500-D03
2.0
[03] PROCESSOR 2/7
A4
344Thursday, March 24, 2016
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
6-7P-N6505-005
R89 100_1%_04
R97 *1K_04
R508 49.9_1%_04
R96 *1K_04
R521 2.74K_1%_04
R88 56.2_1%_04
R98 *1K_04
SKL_S_CPU
LGA1151
5 OF 12
REV = 1.2
U1E
3H993921-4M41-02H
PCI_BCLKP
W1
VIDSCK
E38
CATERR#
D13
PROC_SELECT#
AB36
SKTOCC#
AB35
ZVM#
AC38
DDR_VTT_CNTL
AC36
VIDSOUT
E40
CLK24P
K9
CLK24N
J9
CFG_RCOMP
M11
PROC_PRDY#
B10
PROC_PREQ#
B9
PROC_TRST#
F12
PROC_TCK
F11
PROC_TMS
F13
PROC_TDI
G12
PROC_TDO
H13
BPM#[3]
H14
BPM#[2]
G14
BPM#[1]
D17
BPM#[0]
D16
CFG[18]
G18
CFG[17]
F14
CFG[15]
H19
CFG[14]
F21
CFG[13]
F20
CFG[12]
G20
CFG[11]
H17
CFG[10]
F17
CFG[9]
E16
CFG[8]
G16
CFG[7]
H20
CFG[5]
H18
CFG[6]
G21
CFG[4]
F19
CFG[3]
H16
CFG[2]
F16
CFG[1]
F15
CFG[0]
H15
PCI_BCLKN
W2
BCLKN
W4
BCLKP
W5
THERMTRIP#
D11
PECI
G7
PM_DOWN
D8
PM_SYNC
E8
RESET#
E7
PROCPWRGD
F8
PROCHOT#
C39
VCCST_PWRGD
U2
RSVD_AC37
AC37
CFG[19]
F18
CFG[16]
E14
VIDALERT#
E39
Q5
2SK3018S3
G
DS
R87 100_04
R100 *1K_04
R101 *1K_04
R95 *1K_04
R99 *1K_04
R94 1K_1%_04
C54
47P_50V_NPO_04
R103 560_04
R110 51_04
R86 75_1%_04
R93 *10mil_short
R499 20_1%_04
R517 *10mil_short
R522 6.04K_1%_04
R63
100K_04
R107 51_04
R92 *10mil_short
R510 10K_04
R91 220_04
H_PRDY_N
H_PREQ_N
H_TRST_N
H_TCK
H_TMS
H_TDI
H_TDO
H_SKTOCC_N
H_PROCHOT_R_N
H_PM_SYNC
CFG_RCOMP
CFG_STRAP_6
CFG7
CFG0
CFG2
CFG_STRAP_4
CFG_STRAP_5
CFG9
H_VIDSOUT
CPU_VIDALERT_N
H_VIDSCK
H_VIDALERT_N_VR
H_VIDSOUT
DDR_VTT_CNTL
TP_RSCD_AC37
FM_OPC_ZVM_N
VCCST_PWRGD_CPU
H_PWRGD
H_PM_DOWN_R
H_PECI
H_PROCHOT_N
H_THERMTRIP_N
H_THERMTRIP_N
H_SKTOCC_N
H_TCK
H_TDO
H_PROCHOT_N