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Compaq Deskpro 4000 User Manual

Compaq Deskpro 4000
226 pages
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Technical
Reference
Guide
for
Compaq Deskpro 4000 and 6000 Personal Computers
featuring the Pentium II Processor

Table of Contents

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Compaq Deskpro 4000 Specifications

General IconGeneral
BrandCompaq
ModelDeskpro 4000
CategoryDesktop
LanguageEnglish

Summary

Chapter 2 SYSTEM OVERVIEW

2.2.1 STANDARD FEATURES

Lists the core features included in all models of the computers.

2.4 SYSTEM ARCHITECTURE

Explains the system's architecture, buses, and key components.

2.4.1 PENTIUM II PROCESSOR

Describes the Pentium II processor, its cartridge, and cache.

2.4.2 MEMORY

Details system memory, DIMM sockets, SDRAM, and ROM components.

2.4.3 SUPPORT CHIPSET

Lists chipsets used on the system board and their functions.

2.4.4 NETWORK INTERFACE

Covers the integrated network interface controller and its features.

2.4.5 GRAPHICS SUBSYSTEM

Explains graphics controllers, memory, and resolution differences.

2.4.6 MASS STORAGE

Details diskette and hard drive interfaces and specifications.

2.4.7 SERIAL AND PARALLEL INTERFACES

Covers serial and parallel port functionalities and standards.

2.4.8 UNIVERSAL SERIAL BUS INTERFACE

Describes the USB interface, its speed, and hot-plugging capability.

Chapter 3 PROCESSOR/MEMORY SUBSYSTEM

3.2 PENTIUM II-BASED PROCESSOR/MEMORY SUBSYSTEM

Details the subsystem architecture with Pentium II processor and memory.

3.2.1 PENTIUM II PROCESSOR

Explains the Pentium II processor's SEC cartridge and internal architecture.

3.2.1.1 MMX Technology

Covers MMX instructions for multimedia acceleration and their benefits.

3.2.1.2 PROCESSOR CHANGING/UPGRADING

Discusses considerations for changing or upgrading the processor.

Processor Speed Selection

Explains how DIP switches select bus-to-core frequency for the Pentium II.

3.2.2 SYSTEM MEMORY

Details system memory, DIMM sockets, and SDRAM performance.

3.2.2.1 Memory Changing/Expansion

Guides on installing and expanding system memory with DIMMs.

3.2.3 SUBSYSTEM CONFIGURATION

Lists configuration registers for processor/memory and PCI bus operation.

Chapter 4 SYSTEM SUPPORT

4.2 PCI BUS OVERVIEW

Describes the PCI bus, its implementation, and devices/functions.

4.2.1 PCI CONNECTOR

Details the pinout of the 32-bit PCI bus connector.

4.2.2 PCI BUS MASTER ARBITRATION

Explains the bus master/target arbitration scheme and its signals.

4.2.3 PCI BUS TRANSACTIONS

Covers PCI bus transactions, address/data transfers, and cycle types.

4.2.3.1 I/O and Memory Cycles

Details I/O and memory cycles and addressing.

4.2.3.2 Configuration Cycles

Explains PCI configuration cycles and registers.

4.2.5 PCI INTERRUPT MAPPING

Details PCI interrupt signal routing and sharing with ISA interrupts.

4.2.6 PCI CONFIGURATION

Covers PCI configuration parameters handled by the PCI/ISA bridge.

4.3 AGP BUS OVERVIEW

Describes the Accelerated Graphics Port (AGP) bus and its features.

4.3.1 AGP CONFIGURATION

Explains AGP bus interface configuration using PCI registers.

4.4 ISA BUS OVERVIEW

Describes the Industry Standard Architecture (ISA) bus for I/O peripherals.

4.4.2 ISA BUS TRANSACTIONS

Covers ISA bus transfer rates, addressing, and control signals.

4.4.3 DIRECT MEMORY ACCESS

Explains Direct Memory Access (DMA) for ISA devices.

4.4.3.1 Page Registers

Details DMA page registers for defining the complete address for DMA channels.

4.4.3.2 DMA Controller Registers

Lists DMA controller registers and their I/O port addresses.

4.4.4 INTERRUPTS

Discusses microprocessor interrupts: maskable and nonmaskable.

4.4.4.1 Maskable Interrupts

Explains maskable interrupts, signal routing, and priorities.

4.4.4.2 Non-Maskable Interrupts

Covers non-maskable interrupts (NMI, SMI) generation and status.

4.4.5 INTERVAL TIMER

Details the interval timer function, counters, and registers.

4.4.6 ISA CONFIGURATION

Discusses ISA configuration parameters managed by the PCI/ISA bridge.

4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY

Covers RTC and configuration memory functions provided by the I/O controller.

4.6.1 CONFIGURATION MEMORY BYTE DEFINITIONS

Maps configuration memory locations to specific functions and default values.

4.7 I/O MAP AND REGISTER ACCESSING

Provides system I/O map and register accessing methods.

4.7.1 SYSTEM I/O MAP

Lists system I/O ports and their associated functions.

4.7.2 87307 I/O CONTROLLER CONFIGURATION

Explains 87307 I/O controller configuration and PnP registers.

4.8 SYSTEM MANAGEMENT SUPPORT

Covers hardware support for security, identification, and power.

4.8.1 FLASH ROM WRITE PROTECT

Explains flash ROM write protection and security features.

4.8.2 PASSWORD PROTECTION

Details power-on and administrator password protection mechanisms.

4.8.3 I/O SECURITY

Describes how I/O functions can be disabled via configuration registers.

4.8.4 USER SECURITY

Covers QuickLock and QuickBlank features for user security.

4.8.5 TEMPERATURE SENSING

Explains temperature sensors and their role in system shutdown.

4.8.8 POWER MANAGEMENT

Covers Advanced Power Management (APM) firmware and software support.

Chapter 5 INPUT/OUTPUT INTERFACES

5.2 ENHANCED IDE INTERFACE

Covers the EIDE interface, controllers, and supported devices.

5.2.1 IDE PROGRAMMING

Explains IDE interface configuration and control via registers.

5.2.1.1 IDE Configuration Registers

Lists PCI configuration registers for the IDE controller.

5.2.1.2 IDE Bus Master Control Registers

Details IDE bus master control registers.

5.2.1.3 IDE ATA Control Registers

Describes ATA control registers for drives and interface mapping.

5.3 DISKETTE DRIVE INTERFACE

Covers the diskette drive interface and its operational phases.

5.3.1 DISKETTE DRIVE PROGRAMMING

Explains diskette drive configuration and activation.

5.3.1.1 Diskette Drive Interface Configuration

Lists PnP configuration registers for the diskette drive interface.

5.3.1.2 Diskette Drive Interface Control

Details diskette drive interface control via I/O registers.

5.4.3.2 Serial Interface Control

Details serial interface control via registers and BIOS functions.

5.5.4.2 Parallel Interface Control

Covers parallel interface control via BIOS functions and registers.

5.6.3.2 8042 Control

Covers 8042 control functions using I/O mapped ports.

5.8.2 USB CONTROL

Covers USB control via I/O registers.

Chapter 6 AUDIO SUBSYSTEM

6.2.1 PCM AUDIO PROCESSING

Explains Pulse Code Modulation (PCM) for audio processing.

6.3.2 CONTROL

Details control of the audio subsystem via I/O mapped registers.

Chapter 7 POWER SUPPLY AND DISTRIBUTION

7.2.2 POWER CONTROL

Explains power control via the PS On signal and power button operations.

Chapter 8 BIOS ROM

8.3 ACCESSING CONFIGURATION MEMORY

Describes BIOS functions for accessing CMOS and NVRAM.

8.6 POWER MANAGEMENT SUPPORT

Explains Advanced Power Management (APM) BIOS support.

Appendix A ERROR MESSAGES AND CODES

A.13 HARD DRIVE ERROR MESSAGES (17xx-xx)

Lists hard drive error messages and their probable causes.

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