Home
Cypress
Controller
CY7C68013
Cypress CY7C68013 User Manual
4
of 1
of 1 rating
48 pages
Give review
Manual
Specs
To Next Page
To Next Page
To Previous Page
To Previous Page
Loading...
CY7C68013
Docum
ent #: 38
-08012
Rev
. *A
Page 21
of 48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/F
D13
PD6/F
D14
PD7/F
D15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLW
R
AVCC
XTALO
UT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
IFCLK
RESE
RVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD4/
FD12
PD3/
FD11
PD2/
FD10
PD1/F
D9
PD0/F
D8
*WAKEU
P
VCC
RESET#
GND
PA7/*FL
AGD/SLCS
#
PA6/PKT
END
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*
WU2
PA2/*S
LOE
PA1/IN
T1#
PA0/IN
T0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD
7
PB6/FD
6
PB5/FD
5
PB4/FD
4
CY7C
68013
56-pin SSOP
Figure 4-4. C
Y7C6801
3 56-pin SSO
P Pin Assignmen
t
* deno
tes program
mable p
olarity
20
22
Table of Contents
Default Chapter
2
Table of Contents
2
1 Ez-Usb® Fx2™ Features
5
Figure 1-1. Block Diagram
5
2 Applications
6
3 Functional Overview
6
USB Signaling Speed
6
8051 Microprocessor
6
I 2 C-Compatible Bus
7
Buses
7
USB Boot Methods
8
Renumeration
8
Interrupt System
8
Table 3-1. Default ID Values for FX2
8
Table 3-2. INT2 USB Interrupts
9
Reset and Wakeup
10
Program/Data RAM
10
Table 3-3. Individual FIFO/GPIF Interrupt Sources
10
Figure 3-1. Internal Code Memory, EA = 0
11
Figure 3-2. External Code Memory, EA = 1
12
Register Addresses
13
Endpoint RAM
13
Figure 3-3. Endpoint Configuration
14
Table 3-4. Default Full-Speed Alternate Settings [1, 2]
14
External FIFO Interface
15
Gpif
15
Table 3-5. Default High-Speed Alternate Settings [1, 2]
15
USB Uploads and Downloads
16
Autopointer Access
16
I 2 C-Compatible Controller
16
4 Pin Assignments
17
Table 3-6. Strap Boot EEPROM Address Lines to These Values
17
Figure 4-1. Signals
18
Figure 4-2. CY7C68013 128-Pin TQFP Pin Assignment
19
Figure 4-3. CY7C68013 100-Pin TQFP Pin Assignment
20
Figure 4-4. CY7C68013 56-Pin SSOP Pin Assignment
21
CY7C68013 Pin Descriptions
22
Table 4-1. FX2 Pin Descriptions [5]
22
5 Register Summary
29
Table 5-1. FX2 Register Summary
29
6 Absolute Maximum Ratings
35
7 Operating Conditions
35
600 DC Characteristics
35
Table 8-1. DC Characteristics
35
Table 8-2. USB Transceiver
35
9 Ac Electrical Characteristics
36
USB Transceiver
36
Program Memory Read
36
Figure 9-1. Program Memory Read Timing Diagram
36
Table 9-1. Program Memory Read Parameters
36
Data Memory Read
37
Figure 9-2. Data Memory Read Timing Diagram
37
Table 9-2. Data Memory Read Parameters
37
Data Memory Write
38
Figure 9-3. Data Memory Write Timing Diagram
38
Table 9-3. Data Memory Write Parameters
38
GPIF Synchronous Signals
39
Figure 9-4. GPIF Synchronous Signals Timing Diagram [12]
39
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK [13, 14]
39
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced
39
Slave FIFO Synchronous Read
40
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram [12]
40
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
40
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
40
Slave FIFO Asynchronous Read
41
Slave FIFO Synchronous Write
41
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram [12]
41
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram [12]
41
Table 9-8. Slave FIFO Asynchronous Read Parameters [15]
41
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
41
Slave FIFO Asynchronous Write
42
Slave FIFO Synchronous Packet End Strobe
42
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram [12]
42
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram [12]
42
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
42
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
42
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters
42
Slave FIFO Asynchronous Packet End Strobe
43
Slave FIFO Output Enable
43
Slave FIFO Address to Flags/Data
43
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram [12]
43
Figure 9-11. Slave FIFO Output Enable Timing Diagram [12]
43
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram [12]
43
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters
43
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters [15]
43
Table 9-15. Slave FIFO Output Enable Parameters
43
Slave FIFO Synchronous Address
44
Slave FIFO Asynchronous Address
44
10 Ordering Information
44
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram
44
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram [12]
44
Table 9-16. Slave FIFO Address to Flags/Data Parameters
44
Table 9-17. Slave FIFO Synchronous Address Parameters [14]
44
Table 9-18. Slave FIFO Asynchronous Address Parameters [15]
44
Table 10-1. Ordering Information
44
11 Package Diagrams
45
Figure 11-1. 56-Lead Shrunk Small Outline Package O56
45
Figure 11-2. 100-Pin Thin Plastic Quad Flatpack (14 X 20 X 1.4 MM) A101
46
Figure 11-3. 128-Lead Thin Plastic Quad Flatpack (14 X 20 X 1.4 MM) A128
47
4
Based on 1 rating
Ask a question
Give review
Questions and Answers:
Need help?
Do you have a question about the Cypress CY7C68013 and is the answer not in the manual?
Ask a question
Cypress CY7C68013 Specifications
General
Brand
Cypress
Model
CY7C68013
Category
Controller
Language
English
Related product manuals
CapSense Express CY8CMBR3108
167 pages
Cypress EZ-USB CX3
35 pages
Cypress EZ-USB FX2LP
42 pages
To Next PageTo Next PageTo Previous PageTo Previous Page
Loading...
Need help?
General
