Cypress CY7C68013 User Manual

CY7C68013
Document #: 38-08012 Rev. *A Page 22 of 48
4.1 CY7C68013 Pin Descriptions
Table 4-1. FX2 Pin Descriptions
[5]
128 100 56 Name Type Default Description
10 9 10 AVCC Power N/A Analog V
CC
. This signal provides power to the analog section of the
chip.
13 12 13 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible.
19 18 16 DPLUS I/O/Z Z USB D– Signal. Connect to the USB D– signal.
18 17 15 DMINUS I/O/Z Z USB D+ Signal. Connect to the USB D+ signal.
94 A0 Output L 8051 Address Bus. This bus is driven at all times. When the 8051
is addressing internal RAM it reflects the internal address.
95 A1 Output L
96 A2 Output L
97 A3 Output L
117 A4 Output L
118 A5 Output L
119 A6 Output L
120 A7 Output L
126 A8 Output L
127 A9 Output L
128 A10 Output L
21 A11 Output L
22 A12 Output L
23 A13 Output L
24 A14 Output L
25 A15 Output L
59 D0 I/O/Z Z 8051 Data Bus. This bidirectional bus is high-impedance when inac-
tive, input for bus reads, and output for bus writes. The data bus is
used for external 8051 program and data memory. The data bus is
active only for external bus accesses, and is driven LOW in suspend.
60 D1 I/O/Z Z
61 D2 I/O/Z Z
62 D3 I/O/Z Z
63 D4 I/O/Z Z
86 D5 I/O/Z Z
87 D6 I/O/Z Z
88 D7 I/O/Z Z
39 PSEN# Output H Program Store Enable. This active-LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x2000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
34 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when the 8051 address bus
matches the BPADDRH/L registers and breakpoints are enabled in
the BREAKPT register (BPEN = 1). If the BPPULSE bit in the
BREAKPT register is HIGH, this signal pulses HIGH for eight
12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal re-
mains HIGH until the 8051 clears the BREAK bit (by writing 1 to it) in
the BREAKPT register.
99 77 49 RESET# Input N/A Active LOW Reset. Resets the entire chip. This pin is normally tied
to V
CC
through a 100K resistor, and to GND through a 0.1-µF capac-
itor.
Note:
5. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and
in standby.

Cypress CY7C68013 Specifications

General

Brand	Cypress
Model	CY7C68013
Category	Controller
Language	English