Cypress CY7C68013 User Manual

CY7C68013
Document #: 38-08012 Rev. *A Page 23 of 48
35 EA Input N/A External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051 fetches
this code from its internal RAM. IF EA = 1 the 8051 fetches this code
from external memory.
12 11 12 XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and 20-pF capacitor to GND.
It is also correct to drive XIN with an external 24 MHz square wave
derived from another clock source.
11 10 11 XTALOUT Output N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and 20-pF capacitor to GND.
If an external clock is used to drive XIN, leave this pin open.
1 100 5 CLKOUT O/Z 12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock.
The 8051 defaults to 12-MHz operation. The 8051 may three-state
this output by setting CPUCS.1 = 1.
Port A
82 67 40 PA0 or
INT0#
I/O/Z I
(PA0)
Multiplexed pin whose function is selected by:
PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83 68 41 PA1 or
INT1#
I/O/Z I
(PA1)
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
84 69 42 PA2 or
SLOE
I/O/Z I
(PA2)
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPOLAR.4) for the slave FIFOs connected to FD[0..7] or
FD[0..15].
85 70 43 PA3 or
WU2
I/O/Z I
(PA3)
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts up
the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Asserting this pin inhibits the chip from suspending, if
WU2EN=1.
89 71 44 PA4 or
FIFOADR0
I/O/Z I
(PA4)
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs con-
nected to FD[0..7] or FD[0..15].
90 72 45 PA5 or
FIFOADR1
I/O/Z I
(PA5)
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs con-
nected to FD[0..7] or FD[0..15].
91 73 46 PA6 or
PKTEND
I/O/Z I
(PA6)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input-only packet end with programmable polarity
(FIFOPOLAR.5) for the slave FIFOs connected to FD[0..7] or
FD[0..15].
Table 4-1. FX2 Pin Descriptions
[5]
(continued)
128 100 56 Name Type Default Description

Cypress CY7C68013 Specifications

General

Brand	Cypress
Model	CY7C68013
Category	Controller
Language	English