Cypress CY7C68013 - Data Memory Write

CY7C68013
Document #: 38-08012 Rev. *A Page 38 of 48
9.4 Data Memory Write
Table 9-3. Data Memory Write Parameters
Parameter Description Min. Max. Unit Notes
t
AV
Delay from Clock to Valid Address 0 10.7 ns
t
STBL
Clock to WR Pulse LOW 0 11.2 ns
t
STBH
Clock to WR Pulse HIGH 0 11.2 ns
t
SCSL
Clock to CS Pulse LOW 13.0 ns
t
ON1
Clock to Data Turn-on 0 13.1 ns
t
OFF1
Clock to Data Hold Time 0 13.1 ns
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
t
STBL
t
STBH
data out
t
OFF1
CLKOUT
A[15..0]
WR#
t
AV
D[7..0]
t
CL
data out
Stretch = 1
t
ON1
t
SCSL
t
AV
CS#
t
ON1
CS#
Figure 9-3. Data Memory Write Timing Diagram