Cypress CY7C68013 - Slave FIFO Asynchronous Packet End Strobe; Slave FIFO Output Enable; Slave FIFO Address to Flags;Data

CY7C68013
Document #: 38-08012 Rev. *A Page 43 of 48
9.11 Slave FIFO Asynchronous Packet End Strobe
9.12 Slave FIFO Output Enable
9.13 Slave FIFO Address to Flags/Data
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
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Parameter Description Min. Max. Unit
t
IFCLK
IFCLK Period 20.83 200 ns
t
SPE
PKTEND to Clock Set-up Time 8.6 ns
t
PEH
Clock to PKTEND Hold Time 2.5 ns
t
XFLG
Clock to FLAGS Output Propagation Delay 13.5 ns
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters
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Parameter Description Min. Max. Unit
t
PEpwl
PKTEND Pulse Width LOW 50 ns
t
PWpwh
PKTEND Pulse Width HIGH 50 ns
t
XFLG
PKTEND to FLAGS Output Propagation Delay 70 ns
Table 9-15. Slave FIFO Output Enable Parameters
Parameter Description Min. Max. Unit
t
OEon
SLOE Assert to FIFO DATA Output 10.5 ns
t
OEoff
SLOE Deassert to FIFO DATA Hold 10.5 ns
FLAGS
t
XFLG
PKTEND
t
PEpwl
t
PEpwh
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
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SLOE
DATA
t
OEon
t
OEoff
Figure 9-11. Slave FIFO Output Enable Timing Diagram
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FIFOADR [1.0]
DATA
t
XFLG
t
XFD
FLAGS
NN+1
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram
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