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CY7C68013
Cypress CY7C68013 User Manual
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CY7C68013
Docum
ent #: 38
-08012
Rev
. *A
Page 18
of 48
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
56
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
TIME
R2
TIME
R1
TIME
R0
100
D7
D6
D5
D4
D3
D2
D1
D0
EA
128
RD#
WR#
CS#
OE#
PSEN#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
IFCLK
CLKOUT
DPLUS
DMINUS
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLC
S#
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
Port
GPIF Mas
ter
Slav
e FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
Figure 4-1. Sig
nals
17
19
Table of Contents
Default Chapter
2
Table of Contents
2
1 Ez-Usb® Fx2™ Features
5
Figure 1-1. Block Diagram
5
2 Applications
6
3 Functional Overview
6
USB Signaling Speed
6
8051 Microprocessor
6
I 2 C-Compatible Bus
7
Buses
7
USB Boot Methods
8
Renumeration
8
Interrupt System
8
Table 3-1. Default ID Values for FX2
8
Table 3-2. INT2 USB Interrupts
9
Reset and Wakeup
10
Program/Data RAM
10
Table 3-3. Individual FIFO/GPIF Interrupt Sources
10
Figure 3-1. Internal Code Memory, EA = 0
11
Figure 3-2. External Code Memory, EA = 1
12
Register Addresses
13
Endpoint RAM
13
Figure 3-3. Endpoint Configuration
14
Table 3-4. Default Full-Speed Alternate Settings [1, 2]
14
External FIFO Interface
15
Gpif
15
Table 3-5. Default High-Speed Alternate Settings [1, 2]
15
USB Uploads and Downloads
16
Autopointer Access
16
I 2 C-Compatible Controller
16
4 Pin Assignments
17
Table 3-6. Strap Boot EEPROM Address Lines to These Values
17
Figure 4-1. Signals
18
Figure 4-2. CY7C68013 128-Pin TQFP Pin Assignment
19
Figure 4-3. CY7C68013 100-Pin TQFP Pin Assignment
20
Figure 4-4. CY7C68013 56-Pin SSOP Pin Assignment
21
CY7C68013 Pin Descriptions
22
Table 4-1. FX2 Pin Descriptions [5]
22
5 Register Summary
29
Table 5-1. FX2 Register Summary
29
6 Absolute Maximum Ratings
35
7 Operating Conditions
35
600 DC Characteristics
35
Table 8-1. DC Characteristics
35
Table 8-2. USB Transceiver
35
9 Ac Electrical Characteristics
36
USB Transceiver
36
Program Memory Read
36
Figure 9-1. Program Memory Read Timing Diagram
36
Table 9-1. Program Memory Read Parameters
36
Data Memory Read
37
Figure 9-2. Data Memory Read Timing Diagram
37
Table 9-2. Data Memory Read Parameters
37
Data Memory Write
38
Figure 9-3. Data Memory Write Timing Diagram
38
Table 9-3. Data Memory Write Parameters
38
GPIF Synchronous Signals
39
Figure 9-4. GPIF Synchronous Signals Timing Diagram [12]
39
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK [13, 14]
39
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced
39
Slave FIFO Synchronous Read
40
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram [12]
40
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
40
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
40
Slave FIFO Asynchronous Read
41
Slave FIFO Synchronous Write
41
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram [12]
41
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram [12]
41
Table 9-8. Slave FIFO Asynchronous Read Parameters [15]
41
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
41
Slave FIFO Asynchronous Write
42
Slave FIFO Synchronous Packet End Strobe
42
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram [12]
42
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram [12]
42
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
42
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
42
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters
42
Slave FIFO Asynchronous Packet End Strobe
43
Slave FIFO Output Enable
43
Slave FIFO Address to Flags/Data
43
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram [12]
43
Figure 9-11. Slave FIFO Output Enable Timing Diagram [12]
43
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram [12]
43
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters
43
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters [15]
43
Table 9-15. Slave FIFO Output Enable Parameters
43
Slave FIFO Synchronous Address
44
Slave FIFO Asynchronous Address
44
10 Ordering Information
44
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram
44
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram [12]
44
Table 9-16. Slave FIFO Address to Flags/Data Parameters
44
Table 9-17. Slave FIFO Synchronous Address Parameters [14]
44
Table 9-18. Slave FIFO Asynchronous Address Parameters [15]
44
Table 10-1. Ordering Information
44
11 Package Diagrams
45
Figure 11-1. 56-Lead Shrunk Small Outline Package O56
45
Figure 11-2. 100-Pin Thin Plastic Quad Flatpack (14 X 20 X 1.4 MM) A101
46
Figure 11-3. 128-Lead Thin Plastic Quad Flatpack (14 X 20 X 1.4 MM) A128
47
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Cypress CY7C68013 Specifications
General
Brand
Cypress
Model
CY7C68013
Category
Controller
Language
English
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