Datron 1061 - Page 32

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24
3.2.3.4
Hish
Speed
Buffer
C22
slows
the
switching
edges
from
the
multiplexer
M35
so
that
the
buffer
cannot slew-limit
and
thus
lose
the
charge.
The
signals
are fed
to 036, M34
which
comprise
a
high
speed
buffer
with
high
common
mode
rejection
ratio
(See
Fig.
3.16).
The common
mode
rejection
is
dependent
on
the
power
supplies of
036
(from
R66
and
R11-R15)
being
bootstrapped to the
output
of
the
buffer,
via
D2
and
D4. Thus
the difference
between
input
signal
and
power
supply around
the
input
stage
is
maintained
constani
whatever the
input
signal.
3.2.3.5
lntegrator
The
basic lntegrator
comprises
R6,
R7
and
C9,
with
hybrid
amplifier
O35 and
M25.
(See
Fig. 3.17).
Low-noise
FÊT-pair
O35
also
has low
gate
leakage,
which
maintains
the
effectiveness
of 'sample-and-hold'
components
R34
and
C12.
An inverted
and
attenuated
version of
the
integrator
output
voltage
is developed
across
R5'
This
is applied
via
R4
and
C10
to compensate
for
the
small
amount
of
dielectric
absorption
in C9.
The
value
of
R5
is
factory'
selected
to
equalize
readings
of
the
same
input,
taken
at
differing
read-rates
(including'one'shot'
measurements)'
Cl1
and
R27
provide shorter
term
compensation,
R23
being
set
to
correct
linearity
at
10%
of
full range'
R12l
R11
M34
+
R35
R66
036
R36
Fig.
3.16
HIGH SPEED
BUFFER
CIRCUITRY
D4
c18
o3
R15/R14
c22
R8
o1
o4
+
c19
+
D2
R10
TP5
-15V
To
lntegrator
From
Multiplexer
M35
rl/¡22
+
R25
M25
o35
R31R33
R26
R23
cl2
R32
R6/R7
R59
R28
c9
+
R34
From
-1
R4
c10
c11
R27
Fig.
3.17 INTEGRATOR
ClRCUlr
To
znd Null
Detector
R5
FSV
..
..1.
'
Hi,-,1i,'
ti,-,,,,,
:
i,'**;r"-i''1
'.,'..
-
.
,,
"
,'t
,-tlri
:.-. :'
.i'.i
.'-,
"