Datron 1061 - 3.8.1.3 Ram;Rom; Cmos

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36
3.8.1.3
RAM/ROM
Circuit
The
6800 uses 3
Read-Only
Memory
chips
(ROMs)
which
contain the
program
necessary
to
run
the
instrument.
Each
ROM
is
able
to store
up
to
4096,
8'bit
'bytes'
of
program
information;
grouped
in
program modules.
The
MPU accesses
a byte
by
placing
its
address
on
the 16'bit
Address
Bus and
driving
the Valid
Memory
Address
(VMA)
j line
true
(logic-1).
The
information
held
in that
particular
.-
,
location
is then
sent
back to
the
MPU
via
the Processor
Data
Bus.
The
chip-select
inputs
for the RAM
and
ROM
are
decoded
from
a
selection
of
high'order
address
bits. This
selection
determines
the
positions
of
the RAM and ROM
in the
memory
map.
For example:
M30 is
fed from
A1
5.413.A12
so
that
it covers
the memory locations from
#F000
to
#FFFF
(Note
that since 414 is not
decoded
M30
also
appears
at
#8000
to
#BFFF).
The
processor
employs
1024 bytes
of 8-bit wide
Random
Access
Memory
(RAM)
made
up
from
two 1024
x
4-bit
RAMs
(M31/M36).
M31 and
M36
are employed
as
operating
memory
for scratch
pad
operations
and
storing
volatile
data
(e.g.
Max,
Min). The
principal
location
of
the
RAM
is
from *Ð000
to
*ÐOFF.
Since
A8
and
Ag
are not
decoded
there
are
images
start¡ng
at
*o100,
#0200,
#0300.
A
further
256
bytes of 8-bit
wide
RAM
are
made up
from
two
256
x
4-bit
RAMs
(M19/M20).
M19
and
M20 are
backed
up
by
a
battery
to
privide
the
non-volatile
'Calib-
ration'
and'Zero'
memory.
Three
address
bits
412, 414
and
Ã15
are
decoded
by M33
(pin
8)
to enable
M19/M20,
but
M2g
(pin
6)
permits the memory
contents
to
be
changed
only
íf
CAL
is
selected,
or
if
the
ZERO
section
of
the
effect
of
this
and
the
800kHz
output
from
M57-15
is
to
'stretch'
the
waveforms
of
the Phase
1
and 2 clock
outputs
(illustrated
in
Fig.
3.36).
Thus
phase
2 remains
at
logic
1
for 1% cycles
of the
normal
800kHz operation,
allowing
more
time
for
CMOS
transfers.
memory
is addressed
(47
and A6
both at
logic-11.
The
read/ñIrite
control
line R/W
from the
6800
is
gated
with
a'Master
Clock
+ 2'signal
to
provide correct
ilring,
and
the address
decodes
include
gating
with
VMAø2'
An
instrument
power
up-is
dltected
by
M60/M62
causing
an
initializat¡on
RfSgT
signal
to be
fed to
the
MPU
via
016.
(See
Fis. 3.38).
During
a
power-up
or
power'dow¡
(+5V
supply
line
(+4.75V)
a
signal
from the
supply-level
detectors
prevents
RAMs
M19
and
M20
from
being
overwritten
by holding
the
CS
(chip
select)
lines
low
(<0.2
volts)
via 014
for a
period
of
approx.
25mS
determined
by
R55/C32.
3.8.2
CMOS
Address
Decode
and
lnput/Output
Circuits
(430329
sheet
2)
lnformation
is transferred
to
and
from
CMOS
devices
via
the CMOS
Data
Bus
during
periods
when
the signal
CMOS
l/O
is at
logic'l
(M33-6).
CMOS
l/O
is addressed
when ÃJ8.414.A11
is true.
This
occurs
when
memory
locations
starting
at
#4100
(and
its
images) are
selected'
The
transfer
of
data
between
the
Processor
Data
Bus and
the
CMOS
Data
Bus
takes
place
at
400kHz, the
Read/
Write lines
selecting
the
directíon
of the
information
through
the
tri-state
buffers
M4,
M5 and
M6.
ln order
to
address
the
various
CMOS
input/output
devices,
the
address
lines
must
be
further
decoded. M32
is
a 1-of-10
decoder,
providing
5 addressable
drives; M16
is
a dual
1-of-4
decoder
addressíng
the
front
panel
circuitry
and the
digital
elements
of
the A-D
converter.
A summary
of
the
decoded
CMOS
address
signals
is
given
in Fig. 3.39.
To
account
for
slower
data
transfer
in
CMOS
devices,
the
clock
frequency
is
again
divided
by
two
to
400kHz
when
the
CMOS
data
bui is active.
The
decoded
address
'CMOS
l/O'at
M57-7
is
set to
logic
1
during
these
transfers,
so a 400kHz
square
*.u.
upp"r6
at
M57-1
1.
The
combined
FIG.3.36
TIMING
DIAGRAM
OF STRETCHED
TìA/O'PHASE
CLOCK
M57-15
M57-11
þz
M56-8