Datron 1061 - General Principte; Presetprocedure

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3'8'3
Anarog
to
Dis¡tar
conversion
(Disitar
section)
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is
enabled.
3.8.3.1
Generalprinciple
Block
diagram
Fig.
3.40 outlines
the
essentials
of
the
digital
section
ano
s¡råur¿
o.
,r.O
with
flowchart
Fig'
3.41
in
order
to
follow
the
operation
of
this
section'
The
function
of
this section
of
the
circuitry
is
to
generate
the
sequence
that
when
transferred
to
the
analog
section,
controls
the
sequence from
RESET
through
the
integration
cycle
and
Lack to
RESET.
The
circuitry
controls
the
length
of
SIG and
BIAS
and
counts
during
REF
1
and
REF
2,
the accumulated
count
beíng
proport-
ional
to
the
length
of
the reference
periods,
which
in
turn
is
proportional
to
the
measured
input
signal.
At
the
end
of each
reading
cycle
the count
is
read
by
the
MPU,
pro'
cessed and
displayed.
The sequence
is
controlled
by
stepping
M47
through
O0
to 07. Each
'O'
output
from
M47
goes to
logic-1
to
activate its
stage
of the sequence;
completion
of
one
stage
generates
the
'Enable'
for the
next,
via
M46
switches,
.-
3.8.3.2
Preset Procedure
As
part
of the initialisation
routine
(at
switch
on),
M47
(used
as
the sequence
controller), is reset
from
M3l-
11, causing
M47-2
to be logic'1'.
Thus the
control
lines
A,
B and C
put
the analog
section
of the A-D
into RESET
(See
Fig.
3.42).
The
Address
Bus
decoded
signal
XADDLY
is
taken
low, enabling
the
presett¡ng
of
the delay
counters
M13
and
M14
from
the
CMOS Data Bus. the
amount
of
delay being
determined
by the selected range,
function
and filter state,
see Fi9.3.43.
The
A-D
control
latches,
M11
and M12
are then enabled uy
lÃbcTf-
to
(i)
reset
the
command
latch
Ml
(from
M11-4),
(ii)
set
the resolution
of
the
main
counter
(M11-5
and
6),
(iii)
select
trigger
gate
(M12-3,
4 or 5)
and
(iv)
reset
the
data ready
latch
(M12'6)'
BUFFERS
M24 AM25
PRIMARY
& SECONDARY
COUNTERS
M23
sEo
CONTROLLER
M47/
M46
DATA
READY
LATCH
BUFFERS
M10
INTERRUPT
E RUN/CAL
MESSAGES
NULL
DETECT
LATCH
DELAY
TIMER
DELAY
COUNTERS
M13
I
M14
TRIGGER
CONTROL
A-D CONTROL
LATCHES
M11
eM12
TIMER
CMOS DATA BUS
PROCESSOR
TRIGGER
EXTERNAL
TRIGGER
PROCESSOR
ADDRESS
BUS
8O0 kHz
CLOCK
INTEBNAL
TRIGGER
ANALOG
CONTROL
Nu
ll
Detect
ABC
To DC
lsolator
FIG.3.4O
SIMPLIF¡ED
DIAGRAM
OF DIGITAL
SECTION
OF
A-D
CONVERTER
'...,
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