Datron 1061 - The Two.phase Clock

35
I
Data
Controt:
Data
handled by
the
system
cons¡sts
of
a stream
of
measurement
informatitn
on
which
a
number
of
operations
are
carried
out. A second
stream,
asynchron-
ous
with the
first,
consists
of
commands
derived
from
the
front
panel
or
digital
interface,
controllíng
both
the
measurement
circuits
and
computation
programs'
Oper'
ations
on the
measurement
stream
basically
cons¡st
of
acquiring the
raw
data from
the A-D
converter,
calibrating
this data and
carrying
out any
other
computations,
and
converting
and formatiing
the
iata
for
output'
Note
that
a
job
consuming
data
is
given
higher
priority
than
the
one
producing
data for
it,
allowing a
producer
to
place data
into an empty buffer.
The conzumer
is
activated
by
a
flag,
set
by the
producer
to
indicate
data
ready
in
the
buffer'
Process
Control.
Control
of
the
instrument
by
the
processor,
initiated from
the
front
panel
or
digital
interface,
is
arranged by
using
a
'pipeline
control'
of
the
rnajor
system
state and a
'first in/first out'
buffer
between
the
interrupt
level routine
receiving
the
control
command
and
the main
program
implementing
it. The
major
system
state
consists
of
the range,
function,
resolution,
filter,
ratio,
autorange,
etc.,
flags and the
computation
mode
(reading,
A-8,
+C, etc.).
The
pipeline
comprises
three
levels.
The
top,
level
1, reflects
the
state being
programmed,
the
second,
level 2,
the state
of the
measurement
circuits
and
the third,
level
3, the
measurement
being
processed.
When
a
command
is
input,
level 1
is
updated
(e.g.
a
new
range
is
selected)
and
as
soon as the
measuring
circuits
are
not
converting
an
input
signal,
the
state
in
level
1 is moved
to
level 2
causing
the measurement
circuits
to
update
to the
new state.
When an
A-D
conversion
is
complete,
data
is
read
from the A-D and
the
state
transferred from
level
2
to
3,
providing
information
for
the
processing
rout¡nes.
Additionally,
at this
time,
the
level
1
to
level
2
transfer
is
repeated
and the
measurement
circuits again updated
to
allow
for
commands received
while the conversion
is
in
progress,
A second
control
mechanism
used
is to input
all
the
commands
via a
'first
inÆirst
out' buffer
between
the
interrupt
level
routine
reçeiving
the command
and
the
main
program
implementing it.
Thus the
processor under
remote
control
is
able
to
'simultaneously'
set
up
the
requirements
for the next reading,
convert
the
current
reading
and
process
the last
one.
3.8.1.2
The Two-Phase Clock
The
6800
requires a non-overlapping
positive two-
phase
(Ø1,
Ø2)
clock. This
is
derived
from the
line'locked
master
clock signal
(1.6MHz
for 50Hz line,
1.9MHz
for
60Hz
-
see
sheet
4). The
first
half of M57
divides
the
master
clock
by two
to
800kHz,
producing
antiphase
squarewaves
at
pins
14 and
15. lf data
is
not
being
trans-
ferred via
the CMOS
data
bus; M57
(CMOS
l/O)
is at
logic 0,
M57-11
is at
logic 1, so
M56'8
follows
M57'15.
The circuit
utilizes
the
propagation
delays
inherent
in
M54
and
M55
(approx.
1Ons
per gate),
to ensure
that
the
positive-going
segments
of
Phase
1 and
Phase
2 clock
waveforms
do
not overlap
(as
illustrated
in
Fig. 3-35).
06
and
07 drive
the
clock
output
at
voltage
levels demanded
by
the
processor
(0V
and
+5V).
ji
f
f
f
1:-
t::
1f
$t
From
M56-8
$z
M56-9
M.A4-2
4
4
4
M5,1-3
5
5
þt
M54-11 6
2
b
M55-8
3
3
3
ø2
M54-8
4
4
4
ì
No.
of
ProPagation
DelaYs
FIG. 3.35
TWO-PHASE
CLOCK
GENEBATION
':.
.t.
,.,
.