Datron 1061 - Page 56

44
TP6
PROCESSOR
ADDRESS
BUS
r5V
+5V
øz
XDDSP
<l
DO
Dl
PROCESSOR
DATA
BUS
FIG.3.47
DISPLAY
DRIVER
WRITE
CIRCUITRY
SELECT
M9
B
B
B
2S
3
cso
D5
D1
R/W
D7
M1
RAM
D2
D3
Display
block
energised
or
operation
implemented
from Ml1
1
1
3
5
7
I
1
2
4
6
I
10
Reset Counter
RAM
(M1)
A3
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
t
1
1
COUNTER
(M8)
03
02
01 o0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
3
0
1
1
0
0
1
1
0
0
1
t
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
l.r
,_i,
I
I
'r!.
I
J
-".
Block
Number
+1
2
34s679910
FIG.
3.48
DISPLAY
DRIVER
READ
MODE
ADDRESS
STATES
11