Denon AVR-3312 - Lan8700 (Hdmi: Ic322); LAN8700 Block Diagram

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LAN8700(HDMI:IC322)
LAN8700BlockDiagram
nINT/TX_ER/TXD4
MDC
CRS/PHYAD4
MDIO
nRST
TX_EN
VDD_CORE
VDD33
LINK/PHYAD1
ACTIVITY/PHYAD2
FDUPLEX/PHYAD3
XTAL2
CLKIN/XTAL1
RXD3/nINTSEL
RXD1/MODE1 RXD2/MODE2
TXD3
RX_CLK/REGOFF
TX_CLK
RX_ER/RXD4
VDDIO
TXD1
TXD0
TXD2
COL/RMII/CRS_DV
TXP
RXN VDDA3.3 EXRES1 VDDA3.3 RXP VDDA3.3
USB3300
Hi-Speed USB2
ULPI PHY
32 Pin QFN
1
2
3
4
5
6
7
8
LAN8700/LAN8700I
MII/RMII Ethernet PHY
36 Pin QFN
GND FLAG
10 11 12
13
14 15 16
24
23
22
21
20
19
32 31 30 29
28
SPEED100/PHYAD0 VD_XR9
RXD0/MODE0
17
TXN
18
27
26
25
36 35 34 33
10M Rx
Logic
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
100M PLL
Squelch &
Filters
10M PLL
Receive Section
Central
Bias
HP Auto-MDIX
Management
Control
SMI
RMII / MII Logic
TXP / TXN
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL
/CRS_DV
MDC
MDIO
SPEED100
LINK
ACTIVITY
FDUPLEX
LED Circuitry
MODE Control
nINT
nRST
RXP / RXN
10M Tx
Logic
10M
Transmitter
100M Tx
Logic
100M
Transmitter
Transmit Section
PLL
XTAL1
XTAL2
MODE0
MODE1
MODE2
PHY
Address
Latches
PHYAD[0..4]
Auto-
Negotiation
Interrupt
Generator
MII
MDIX
Control