Denon AVR-3312

194
SAA7121(HDMI:IC323)
SAA7121BlockDiagram
SAA7120
SAA7121
MBH790
1res.
SP
AP
LLC
V
DDD1
V
SSD1
RCV1
RCV2
MP7
MP6
MP5
MP4 MP3 MP2 MP1 MP0
V
DDD2
V
SSD2
RTCI
res.
SA
res.
2
3
4
5
6
7
8
9
10
11
33
V
SSA2
V
SSA1
V
DDA3
V
DDA2
V
DDA1
Y
C
CVBS
res.
res.
res.
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18 19 20
21
22
44 TTX
TTXRQ SDA SCL XCLK XTALI XTALO V
DDD3
V
DDA4
V
SSD3
RESET
43
42 41
40
39 38 37 36
35
34
handbook, full pagewidth
I
2
C-BUS
INTERFACE
DATA
MANAGER
ENCODER
SYNC
CLOCK
OUTPUT
INTERFACE
D
A
40 42 41 21
7
368 43 37 34
35 4
25, 28,
31
MP7
to
MP0
TTX
5, 18, 38
6, 17, 39
1, 20, 22,
23, 26, 29
219 3
30
27
24
32, 33
RESET SDA SCL
RCV1
RCV2
TTXRQ
XCLK
XTALO
XTALI
LLC
V
DDA4
V
SSA1
V
SSA2
SA
CVBS
Y
C
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
V
SSD1,
V
SSD2
,
V
SSD3
V
DDD1,
V
DDD2
,
V
DDD3
V
DDA1,
V
DDA2
,
V
DDA3
res.
SPRTCI AP
clock
and timing
Y
Y
C
CbCr
44
9 to 16
MBH787
SAA7120
SAA7121