Digi ConnectCore User Manual

ConnectCore for i.MX51
©2011DigiInternational,Inc. 51
SPI
The module provides up to three SPI interfaces that can be configured in either master or
slave mode. Two of the SPI interfaces contain one 64 x 32 receive buffer (RXFIFO) and one 64
x 32 transmit buffer (TXFIFO). The other SPI interface contains one 8 x 32 receive buffer and
one 8 x 32 transmit buffer.
Full-duplex synchronous serial interface
Master/Slave configurable
Two SPI interfaces support SPI clocks up to 66MHz in both Master and Slave mode
One SPI interface supports SPI clocks up to 16.5MHz in both Master and Slave mode
Up to four chip selects (two chip select for SPI1) to support multiple peripherals
Transfer continuation function allows unlimited length data transfers
Polarity and phase of the chip select (SS#) and SPI Clock (SCLK) are configurable
Data ready output signal for fast data communication with fewer software interrupts
DMA support
Watchdog Timer
The watchdog timer module protects against system failures by providing a method of
escaping from unexpected events or programming errors. Once the watchdog module is
activated, it must be serviced by the software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the watchdog timer module asserts the internal
system reset signal.
A time-out counter with time-out periods from 0.5 to 128 seconds
Time resolution of 0.5 seconds
Configurable time-out counter that can be programmed to run or stop during low-
power and debug modes
Programmable interrupt generation prior to time-out
Programmable time duration between interrupt and timeout events, from 0 to 128
seconds in steps of 0.5 seconds
Power down counter enabled out of any reset by default
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Digi ConnectCore Specifications

General

Brand	Digi
Model	ConnectCore
Category	Control Unit
Language	English