94
LogictableoftheNANDblock:
Input1 Input2 Input3 Input4 Output
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
6.3.4NANDwithedgeevaluation
TheoutputofaNANDwithedgeevaluationisonly1atleastone inputis0and all inputswere1during
thelastcycle.
Theoutputissetto1forthedurationofonecycleandmustberesetto0atleastforthedurationofthe
nextcyclebeforeitcanbesetto1again.
Ablockinputthatisnotused(x)isassigned:x=1.
TimingdiagramofaNANDwithedgeevaluation