EUROCOM M22ES - Page 85

Schematic Diagrams
CPU (Socket 478) 2 of 2 (71-M2200-D06) B - 5
Schematic Diagrams
CPU (Socket 478) 2 of 2
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
+3VS +3VS
3VH8
VCCVID
VCC_CORE
INTR[12]
NMI[12]
DEFER- [4]
HTRDY- [4]
BPRI- [4]
INIT- [12]
STPCLK- [12]
CPUPWRGD [4]
CPURST- [4]
CPUSLP- [12]
SMI- [12]
IGNNE- [12]
A20M- [12]
HDSTBN-[0..3][4]
HASTB-[0..1][4]
DBI-[0..3][4]
HDSTBP-[0..3][4]
FERR- [12]
BNR- [4]
BREQ0- [4]
DBSY- [4]
DRDY- [4]
HLOCK- [4]
HITM- [4]
HIT- [4]
HCLK-CPU#[3]
HCLK-CPU[3]
BSEL0 [3]
BSEL1 [3]
ADS- [4]
OS# [27]
H8_SMDATA[20,28]
H8_SMCLK[20,28]
HTCK
[2]
HBPRM5#
[2]
HBPRM4#
[2]
HBPM1#
[2]
HBPM0#
[2]
HDSTBP-[0..3]
HDSTBN-[0..3]
DBI-[0..3]
HASTB-[0..1]
Z0203
Z0201
FERR-
STPCLK-
INIT-
DBSY-
DRDY-
HTRDY-
ADS-
HLOCK-
BREQ0-
BNR-
HIT-
HITM-
BPRI-
DEFER-
HTCK
HTDI
HTMS
HTRST-
HTDO
PROCHOT-
IGNNE-
SMI-
A20M-
CPUSLP-
CPUPWRGD
CPURST-
THERMDA
THERMDC
THERMTRIP-
DBI-3
DBI-2
DBI-1
DBI-0
HASTB-1
HASTB-0
DBRESET
NMI
INTR
HCLK-CPU#
HCLK-CPU
Z0204
Z0205
HDSTBP-3
HDSTBP-2
HDSTBP-1
HDSTBP-0
HDSTBN-3
HDSTBN-2
HDSTBN-1
HDSTBN-0
Z0208 Z0206
Z0209 Z0207
FERR-
BREQ0-
PROCHOT-
CPUPWRGD
THERMTRIP-
A20M-
STPCLK-
CPUSLP-
SMI-
INIT-
IGNNE-
INTR
NMI
CPURST-
HTDO
HTDI
HTRST-
IERR
IERR
DBRESET
HTMS
TZ0206
TZ0208
TZ0207
TZ0201
TZ0202
TZ0203
Z0202
Z210
Z717
Z240
Z936
THERMDA
Z717
OS#
THERMDC
CPUGTLVREFB
CPUGTLVREFA
H8_SMDATA
H8_SMCLK
H8_SMDATA
H8_SMCLK
HCLK-CPU
HCLK_ITP0
HCLK_ITP0#
HCLK-CPU#
HCLK_ITP0
HCLK_ITP0#
TZ0209
Z241
CPUSLP-
CPUPWRGD
Z0219CPURST-
CPURST-
HTCK
ITP_STPWR
HBPM1#
HBPRM5#
HBPM0#
HBPRM4#
C725
0.0047UF
C367
220PF
C362
47UF
C62
47UF
L63
4.7uH_SMD 30%
1 2
L20
4.7uH_SMD 30%
1 2
C464
0.1UF
C465
0.1UF
C463
0.1UF
C443
220PF
C461
1UF
C453
220PF
C370
220PF
CB1
1UF
R287 51
C432
0.1UF
R268
0(R)
R269 0(R)
C388
0.1UF
C382
0.1UF
C419
0.1UF
C462
0.1UF
R283 51
R294 51
R292 51
T215
R32
51 1%
R316
62 1%
R313
51 1%
R318
62 1%
R262 62 1%
R280
27.4 1%
R315
56 1%
R34
51 1%
R270
56 1%
R317
56 1%
R308 56 1%
R314 75
R86 1.5K
R304
100 1%
R235
100 1%
R264
56 1%
R309 56 1%
R265 56 1%
R33 56 1%
R303
10K
R284 680
R291
150
R236 51.1 1%
R312
51.1 1%
R234
82_1%
R305 82_1%
RP35
4P2RX0(R)
1
23
4
T149
T148
JCPU1B
NORTHWOOD478
AC1
V5
A5
AC26
AD26
AE25
L5
R5
P1
E5
D1
F6 F20 AA6 AA21
W23
P23
J23
F21
W22
R22
K22
E22
AF23
AF22
AC3
V6
B6
Y4
AA3
W5
AB2
H5
H2
J6
G1
G4
H6
G2
F3
E3
D2
E2
D4
C1
F7
E6
D5
B3
C4
A2
C3
B2
B5
C6
AB26
AB23
AB25
A4
V21
P26
G25
E21
C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8
AE23
AD20
AD22
K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
J2 J22 J25 J5 K21 R1 R23
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
G6 R26
E11
E1
F8
G21
G24
T3
T24
T21
G3 R4
AF3
AD6
AD5
L24
AF4
C22
AP0
AP1
VCC_SENSE
ITP_CLK0
ITP_CLK1
DBRESET
ADSTB0
ADSTB1
COMP1
LINT1
LINT0
GTLREF3 GTLREF2 GTLREF1 GTLREF0
STBP3
STBP2
STBP1
STBP0
STBN3
STBN2
STBN1
STBN0
BCLK1
BCLK0
IERR
MCERR
FERR
STPCLK
BINIT
INIT
RSP
DBSY
DRDY
TRDY
ADS
LOCK
BR0
BNR
HIT
HITM
BPRI
DEFER
TCK
TDI
TMS
TRST
TDO
THERMDA
THERMDC
THERMTRIP
PROCHOT
IGNNE
SMI
A20M
SLP
PWRGOOD
RESET
VSS_SENSE
DB#3
DB#2
DB#1
DB#0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VCCIOPLL
VCCA
VSSA
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VCCVIDPRG
BSEL0
BSEL1
COMP0
VCCVID
VSS
R288
40.2 1%
R301
150
C413
0.1UF(0805)
U5
TC1066
15
12
14
6
10
1
5
9
13
16
2
3
4
11
7
8
STBY#
SMBDATA
SMBCLK
ADD1
ADD0
CRIT1/VCC
CRIT0
OS#
NC
NC
GND(VCC)
DXP
DXN
ALERT#
GND
GND
R259 1K
C418
22P
R256 200(0805)
R267 0
R83 10K(R)
R266 1K
TP16
R260 0
R273
4.7K(R)
R82 R
R272
4.7K
R279
0
T143
R274 2.2K
R276 2.2K
T155
T153
T152
T154
T151
T158
C719
0.0047UF
C720
0.0047UF
ITP/TAP TERMINATION
CLOSE TO ITP PORT
CPU SIGNAL TERMINALION
CLOSE TO CPU
CLOSE TO CPU
ITP/TAP TERMINATION
CRIT0
0
0
CRIT1
85
115
1
1
95
0
0
100
X
0
Hardware Protect
=100
度
20 Mils
20 mil
30 mil
20 mil
20 mil
Final ITP Port Define Ready
2001-02-19 am 11:35
Sheet 4 of 31
CPU 2 of 2
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