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FIBOCOM L610 Series Hardware Guide Page 28 of 59
Figure 3-2 Recommended power design
Note:
VBAT_RF and VBAT_BB are included in the subsequent documents.
Power filter capacitor design is shown in the following table:
Reduce power fluctuations during
module operation, requiring low ESR
capacitor
LDO or DCDC power requires not
less than 440uF capacitor
Battery power can be properly
reduced to 100~220uF capacitor
Filter clock and digital signal
interference
Filter low band RF interference
1700/1800/1900, 2100/2300, 2500/2600
MHz band
Filter middle/high band RF
interference
The power stability ensures the normal operation of L610 modules. The design requires special attention
to the power ripple below 300mV (the circuit ESR < 150mΩ). When the module is operating in GSM mode
(Burst transmit), the maximum operating current can reach 2 A, and the power voltage needs to be at
least 3.4 V. Otherwise, the module may power off or restart. The power limit is shown in Figure 3-3: