Chapter 8 Register Structure
Ready/Event send control register (RECR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+H3
- - - - - - - - - - ASE6 ASE5 ASE4 ASE3 ASE2 ASE1
Bit 15-6: Reserved
These bits are reserved. Please set "0" always.
Bit 5-0: Event send request bit (ASE[6:1])
This bit works as an Event send request bit.
Bit5-0: ASE[6:1] Description
0 (1) Request to clear Transmit complete bit (TXC) of Connection n
communication status (CnCSR).
(2) Event send is not done.
(Initial set)
1 Request to execute Event sent to this module.
Exclusive receive control register (EXRR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+H4
- - - - - - - - - - ARP6 ARP5 ARP4 ARP3 ARP2 ARP1
Bit 15-6: Reserved
These bits are reserved. Please set "0" always.
Bit 5-0: Automatic receive mode selective bit (ARP[6:1])
Bit5-0: ARP[6:1] Description
0 ASR connection n is selected Normal mode. (Initial set)
1 ASR connection n is selected Optional mode.
Ready receive control register (RDCR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+H5
- - - - - - - - - -
ARE6 ARE5 ARE4 ARE3 ARE2 ARE1
Bit 15-6: Reserved
These bits are reserved bits. Please set "0" always.
Bit 5-0: Receive Ready bit (ARE[6:1])
This bit is effective to the connection which is declared as the connection on which Automatic Sending/Receiving
function is effective and Exclusive receive control set as enable. Therefore, this bit is ignored when the connection
which is declared as the other condition.
Bit5-0: ARE[6:1] Description
0 (1) Request to clear transmit complete bit (RXC) of Connection n
communication status (CnCSR).
(2) The received data in the buffer of this module is not transmit to receive
area in CPU module. (This data is discarded in this module.)
(Initial set)
1 Request to transmit the data from receive buffer in this module to receive
area of CPU module.
8-9
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