Name: Hitachi H8S/2646
Brand: Hitachi
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1091

C.5 Port 5 Block Diagrams

P5nDDR

WDDR5

WDR5

P5n

RDR5

RPOR5

P5nDR

Reset

Internal data bus

Reset

WDDR5

WDR5

RDR5

RPOR5

n = 0 to 2

: Write to P5DDR

: Write to P5DR

: Read P5DR

: Read port 5

Legend

Figure C-5 (a) Port 5 Block Diagram (Pins P50 to P52)

(H8S/2646, H8S/2646R, H8S/2645)

Default Chapter17
- Table of Contents17
Section 1 Overview33
- Section 1 Overview33
  - Overview33
- Internal Block Diagram38
- Pin Description40
Cpu59
- Overview59
  - Features59
- Differences between H8S/2600 CPU and H8S/2000 CPU60
- Differences from H8/300 CPU61
- Differences from H8/300H CPU61
- CPU Operating Modes62
- Address Space67
- Register Configuration68
- Data Formats73
  - General Register Data Formats73
  - Memory Data Formats75
- Instruction Set76
- Addressing Modes and Effective Address Calculation90
  - Addressing Mode90
  - Effective Address Calculation93
- Processing States97
- Basic Timing103
- Usage Note108
MCU Operating Modes111
- Register Configuration112
- Overview111
  - Operating Mode Selection111
- Register Descriptions112
- Operating Mode Descriptions116
- Address Map in each Operating Mode117
- Pin Functions in each Operating Mode117
Exception Handling121
- Exception Handling Operation122
- Exception Vector Table122
- Overview121
  - Exception Handling Types and Priority121
- Section 4 Exception Handling121
- Reset124
- Traces127
- Interrupts128
- Trap Instruction129
- Stack Status after Exception Handling130
- Notes on Use of the Stack131
Interrupt Controller133
- Block Diagram134
- Pin Configuration135
- Register Configuration135
- Overview133
  - Features133
- Section 5 Interrupt Controller133
- Register Descriptions136
- Interrupt Sources141
- Interrupt Operation146
- Usage Notes155
- DTC Activation by Interrupt157
- Overview161
PC Break Controller (PBC)161
- Register Descriptions163
- Operation167
Bus Controller173
- Block Diagram174
- Pin Configuration175
- Register Configuration175
- Overview173
  - Features173
- Register Descriptions176
- Overview of Bus Control186
- Basic Bus Interface190
- Burst ROM Interface203
- Idle Cycle206
  - Operation206
  - Pin States During Idle Cycles209
- Write Data Buffer Function210
- Bus Arbitration211
- Resets and the Bus Controller212
Data Transfer Controller (DTC)213
- Overview213
- Register Descriptions216
- Operation224
- Interrupts244
- Usage Notes244
I/O Ports245
- Overview245
- Section 9 I/O Ports245
- Port 1253
- Port2264
- Port3274
- Port 4279
- Port 5281
- Port 9285
- Port a287
- Port B293
- Port C298
- Port D303
- Port E308
- Port F313
- Port H319
- Port J321
- Port K324
- Overview327
Section 10 16-Bit Timer Pulse Unit (TPU)327
- Register Descriptions336
- Interface to Bus Master368
  - 16-Bit Registers368
- Operation370
- Interrupts397
- Operation Timing400
  - Input/Output Timing400
  - Interrupt Signal Timing404
- Usage Notes408
- Overview419
Section 11 Programmable Pulse Generator (PPG)419
- Register Descriptions423
- Operation433
- Usage Notes442
- Overview445
Section 12 Watchdog Timer445
- Register Descriptions449
- Operation457
- Interrupts461
- Usage Notes461
- Overview463
Section 13 Serial Communication Interface (SCI)463
- Register Descriptions468
- Operation491
- SCI Interrupts520
- Usage Notes521
- Overview531
Section 14 Smart Card Interface531
- Register Descriptions535
- Operation542
- Usage Notes559
- Overview563
Section 15 Hitachi Controller Area Network (HCAN)563
- Register Descriptions567
- Operation594
- CAN Bus Interface617
- Usage Notes617
- Overview619
Section 16 A/D Converter619
- Register Descriptions623
- Interface to Bus Master629
- Operation630
- Interrupts636
- Usage Notes636
- Overview643
Section 17 Motor Control PWM Timer643
- Register Descriptions648
- Bus Master Interface658
  - 16-Bit Data Registers658
- Operation659
  - PWM Channel 1 Operation659
  - PWM Channel 2 Operation660
- Usage Note661
- Overview663
Section 18 LCD Controller/Driver663
- Register Descriptions666
- Operation673
- Overview685
  - Block Diagram685
  - Register Configuration686
Section 19 RAM685
- Register Descriptions686
  - System Control Register (SYSCR)686
- Operation687
- Usage Notes687
- Features689
Section 20 ROM689
- Overview690
- Pin Configuration697
- Register Configuration698
- Register Descriptions698
- On-Board Programming Modes705
  - Boot Mode705
  - User Program Mode710
- Flash Memory Programming/Erasing712
- Protection721
- Flash Memory Emulation in RAM725
- Flash Memory Programmer Mode727
- Interrupt Handling When Programming/Erasing Flash Memory727
- Flash Memory and Power-Down States741
  - 20.12.1 Notes on Power-Down States741
- Flash Memory Programming and Erasing Precautions742
- Overview747
  - Block Diagram747
  - Register Configuration748
Section 21 Clock Pulse Generator747
- Register Descriptions748
  - System Clock Control Register (SCKCR)748
  - Low-Power Control Register (LPWRCR)749
- Oscillator750
  - Connecting a Crystal Resonator750
- Bus Master Clock Selection Circuit753
- Medium-Speed Clock Divider753
- PLL Circuit753
- Subclock Oscillator754
- Note on Crystal Resonator755
- Subclock Waveform Generation Circuit755
- Overview757
  - Register Configuration761
Section 22 Power-Down Modes757
- Register Descriptions762
- Medium-Speed Mode770
- Sleep Mode771
  - Exiting Sleep Mode771
- Module Stop Mode772
  - Usage Notes773
- Software Standby Mode774
- Hardware Standby Mode777
  - Hardware Standby Mode Timing778
- Watch Mode778
  - Exiting Watch Mode779
  - Notes779
- Sub-Sleep Mode780
  - Exiting Sub-Sleep Mode780
- Sub-Active Mode781
  - 22.10.2 Exiting Sub-Active Mode781
- Clock Output Disabling Function782
- Direct Transitions782
  - 22.11.1 Overview of Direct Transitions782
- Usage Notes783
- Absolute Maximum Ratings785
Section 23 Electrical Characteristics785
- Power Supply Voltage and Operating Frequency Range786
- DC Characteristics787
- AC Characteristics792
- A/D Conversion Characteristics808
- LCD Characteristics809
- Flash Memory Characteristics810
Appendix A Instruction Set813
- Instruction List813
- A.2 Instruction Codes837
- Instruction Codes837
- Operation Code Map852
- Number of States Required for Instruction Execution856
- Bus States During Instruction Execution870
- Condition Code Modification884
- Address890
Appendix B Internal I/O Register890
- B.2 Functions906
- Functions906
Appendix C I/O Port Block Diagrams1107
- C.2 Port 2 Block Diagrams1113
- Port 2 Block Diagrams1113
- C.3 Port 3 Block Diagrams1115
- Port 3 Block Diagrams1115
- C.4 Port 4 Block Diagram1122
- Port 4 Block Diagram1122
- C.5 Port 5 Block Diagrams1123
- Port 5 Block Diagrams1123
- C.6 Port 9 Block Diagram1127
- Port 9 Block Diagram1127
- C.7 Port a Block Diagram1128
- Port a Block Diagram1128
- C.8 Port B Block Diagram1129
- Port B Block Diagram1129
- C.9 Port C Block Diagram1130
- Port C Block Diagram1130
- C.10 Port D Block Diagram1131
- Port D Block Diagram1131
- C.11 Port E Block Diagram1132
- Port E Block Diagram1132
- C.12 Port F Block Diagrams1133
- Port F Block Diagrams1133
- C.13 Port G Block Diagram1140
- Port G Block Diagram1140
- C.14 Port J Block Diagram1141
- Port J Block Diagram1141
- C.15 Port K Block Diagram1142
- Port K Block Diagram1142
Appendix D Pin States1143
Appendix E Timing of Transition to and Recovery1150
Appendix F Package Dimensions1150

Brand	Hitachi
Model	H8S/2646
Category	Desktop
Language	English

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