Chapter 4. Continuous availability and manageability 169
What memory is mirrored
The following areas of memory are mirrored:
Hypervisor data that is mirrored
– Hardware page tables (HPTs) that are managed by the hypervisor on behalf of
partitions to track the state of the memory pages assigned to the partition
– Translation control entries (TCEs) that are managed by the hypervisor on behalf of
partitions to communicate with partition I/O buffers for I/O devices
– Hypervisor code (instructions that make up the hypervisor kernel)
– Memory used by hypervisor to maintain partition configuration, I/O states, virtual I/O
information, partition state, and so on
Hypervisor data that is not mirrored
– Advanced Memory Sharing pool
– Memory used to hold contents of platform dump while waiting for offload to
management console
Partition data that is not mirrored
– Desired memory configured for individual partitions is not mirrored.
To enable mirroring, the requirement is to have eight equally sized functional memory DIMMs
behind at least one POWER7 or POWER7+ chip in each CEC enclosure. The DIMMs will be
managed by the same memory controller. The sizes of DIMMs might be different from one
Power 7 or Power 7+ chip to another.
A write operation in the memory begins on the first DIMM of a mirrored DIMM pair. When
this write is complete, the POWER7 or POWER7+ chip writes the same data to a second
DIMM of the DIMM pair.
The read operations alternate between both DIMMs.
Figure 4-4 shows the hardware implementation of memory mirroring for hypervisor.
Figure 4-4 Hardware implementation of memory mirroring for hypervisor
The impact on performance is low. Whereas writes operations are slightly slower because two
writes are actually done, reads are faster because two sources for the data are used.
DIMMs
Memory controller 0
0
1
2
3
4
5
6
7
Mirrored Data
Data
Memory controller 1
Power7 processor
chip
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