Integra DTR-7.7 - Page 100

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -32
Q8003: IC42S32200L (64-Mbit Synchronous Dynamic RAM)
COLUMN
COUNTER
ADDRESS
BUFFER
A0
A9
BS0
BS1
DQM0~3
CLOCK
BUFFER
COMMAND
DECODER
Sense Amplifier
Row Decoder
Row Decoder
CLK
CKE
CS#
RAS#
CAS#
WE#
DQ0
DQ31
Row Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #2)
DQ
BUFFER
A
10/AP
REFRESH
COUNTER
MODE
REGISTER
CONTROL
SIGNAL
GENERATOR
Column Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #0)
2048 X 256 X 32
CELL ARRAY
(BANK #1)
2048 X 256 X 32
CELL ARRAY
(BANK #3)
Row Decoder
Column Decoder
Column Decoder
Sense Amplifier
Sense Amplifier
Sense Amplifier
Column Decoder
DTR-7.7
BLOCK DIAGRAM