Integra DTR-7.7 - Page 74

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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -6
Q201: CS494003 (DSP)
DTR-7.7
NC5: No connect. Connect to ground.
SD_DATA14, EXTA17: SDRAM data bus output, SRAM external address bus output
SD_DATA15, EXTA18: SDRAM data bus output, SRAM external address bus output
SD_DQM1: SDRAM data mask 1 output.
SD_DATA7, EXTD7: SDRAM data bus. SRAM external data bus input.
SD_DATA6, EXTD6: SDRAM data bus. SRAM external data bus input.
VDDSD4: 3.3V SDRAM / SRAM / EPROM Interface supply
VSSSD4: 3.3V SDRAM / SRAM / EPROM Interface ground.
SD_DATA5, EXTD5: SDRAM data bus. SRAM external data bus input.
SD_DQM0: SDRAM data mask 0 output.
SD_DATA4, EXTD4: SDRAM data bus. SRAM external data bus input.
SD_DATA3, EXTD3: SDRAM data bus. SRAM external data bus input.
UHS0, GPIO18: DSPC control mode select Bit 0, General Purpose I/O
UHS1, GPIO19: DSPC control mode select Bit 1, General Purpose I/O
INTREQ: Control Port Interrupt Request
FA1, FSCDIN
GPIO20: General Purpose I/O can be individually configured and controlled by DSPC.
FAO, FSCCLK
FHS2, FSCDIO, FSCDOUT: Mode select bit 2 or serial control port data input and output,parallel porttype select
GPIO21: General Purpose I/O can be individually configured and controlled by DSPC.
FDAT7: DSPAB Bidirectional Data Bus input
VDD6: 2.5V supply voltage.
VSS6: 2.5V ground.
FHS0, FWR, FDS: Mode select bit 0 or host write strobe or host data strobe
FHS1, FRD, FR/W: Mode select bit 1 or host parallel output enable or host parallel R/W
FDAT6: DSPAB Bidirectional Data Bus input
FCS: Host parallel chip select,Host serial SPI chip select
FINTREQ: Control port interrupt request
FDBCK: Reversed input:This pin is reversed and is pulled up with an external resistor.
FDAT5: DSPAB Bidirectional Data Bus input
FDAT4: DSPAB Bidirectional Data Bus input
VDD7: 2.5V supply voltage.
VSS7: 2.5V ground.
FDAT3: DSPAB Bidirectional Data Bus input
FDBDAReversed input: This pin is reversed and is pulled up with an external resistor.
FDAT2: DSPAB Bidirectional Data Bus input
DBDA: Debug data
DBCK: Debug clock
FDAT1: DSPAB Bidirectional Data Bus input
TEST: This pin is connected low for normal operation.
FDAT0: DSPAB Bidirectional Data Bus input
NV_WE, GPIO16: SRAM write enable output, General Purpose I/O
NV_OE, GPIO15: SRAM output Enable output, General Purpose I/O
NV_CS, GPIO14: SRAM Chip Select output, General Purpose I/O
SD_WE
SD_DATA0, EXTD0: SDRAM data bus. SRAM external data bus input.
SD_DATA1, EXTD1: SDRAM data bus. SRAM external data bus input.
SD_DATA2, EXTD2: SDRAM data bus. SRAM external data bus input.
TERMINAL NAME : DESCRIPTION
: Host Parallel Address Bit Zero or Serial Control Port Clock
: SDRAM write enable output.
: Host parallel address bit zero or SPI rerial control data input
TERMINAL DESCRIPTION (1/3)