Integra DTR-7.7 - Page 84

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -16
DTR-7.7
Q361: CS42528 (8-Ch CODEC with S/PDIF Receiver)
BLOCK DIAGRAM
INT
DAC#1
DAC#2
DAC#5
DAC#4
DAC#3
DAC#6
DAC#7
DAC#8
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OMCK
RMCK
SAI_LRCK
SAI_SCLK
SAI_SDOUT
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
RXP0
RXP1/GPO1
RXP2/GPO2
RXP4/GPO4
RXP3/GPO3
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
MUTEC
FILT+
VQ
REFGND
VA
AGND
AINL+
AINL-
AINR+
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
RST
AD0/CS
TXP VARX AGND LPFLT DGND DGND
VD VD
Analog Filter
Digital Filter
Volume Control
ADC#1
ADC#2
DEM
ADC
Serial
Data
Digital Filter
Digital Filter
Gain & Chip
Gain & Chip
Internal MCLK
CODEC
Serial
Port
Rx
GPO
MUTE
C&U Bit
Data Buffer
Format
Detector
Clock/Data
Recovery
S/P DIF
Decoder
Ref
Control
Port
Mult/Div
Serial
Audio
Interface
Port
PIN CONFIGURATION
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
VARX
AGND
LPFLT
MUTEC
AOUTA1-
AOUTA1+
AOUTB1+
AOUTB1-
AOUTA2-
CX_SDIN2 CX_SDIN3 CX_SDIN4 SAI_SCLK SAI_LRCK OMCK ADCIN1 ADCIN2 CX_SDOUT RMCK SAI_SDOUT VLS DGND VD TXP RXPO
CX_SDIN1
CX_SCLK
CX_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
VQ
FILT+
REFGND
AOUTB4-
AOUTB4+ AOUTA4+
AOUTA4-
VA
AGND
AOUTB3-
AOUTB3+ AOUTA3+
AOUTA3- AOUTB2-
AOUTB2+
AOUTA2+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CS42528