IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -18
DTR-7.7
TERMINAL DESCRIPTION (2/2)
Pin Name
#
Pin Description
VA
VARX
24
41
Analog Power (Input) - Positive power supply for the analog section.
AGND 25
40
Analog Ground (Input) - Ground reference. Connects to analog ground.
MUTEC 38 Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power -on con-
dition or whenever the PDN bit is set to a "1", forcing the codec into power -down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
toy but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
LPFLT 39 PLL Loop Filer (Output) - An RC network should be connected between this pin and ground.
RXP7/GPO7
RXP6/GPO6
RXP5/GPO5
RXP4/GPO4
RXP3/GPO3
RXP2/GPO2
RXP1/GPO1
42
43
44
45
46
47
48
S/PDIF Receiver Input/ General Purpose Output (Input/ Output) - Receiver inputs for S/PDIF encoded
data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the
Receiver Mode Control 2 resister. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
resisters.
RXP0 49 S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
TXP 50 S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the
receiver inputs as indicated by the Receiver Mode Control 2 resister.
VLP 53 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT 54
Serial Audio Interface Serial Data Output (Output) - Output for two's complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
RMCK 55 Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
CX_SDOUT 56 CODEC Serial Data Output (Output) - Output for two's complement serial audio data the internal
and external ADCs.
ADCIN1
ADCIN2
58
57
External ADC Serial Input (Input) - The CS42528 provides for up two external stereo analog to digital
converter inputs to provide a maximum of six channels on serial data output line when the CS42528
is placed in One Line mode.
OMCK
59 External Reference Clock (Input) - External clock reference that must be within the ranges specified in
currently active on the serial audio data line.
SAI_LRCK
60 Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left of Right, is
currently active on the serial audio data line.
SAI_SCLK 61 Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface
Q361: CS42528 (8-Ch CODEC with S/PDIF Receiver)
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