Integra DTR-7.9 - Audio Adjust Functions Overview

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -58
BLOCK DIAGRAM
PIN CONFIGURATION
Q8801: ADV7342 (Video Encoder)
TX-SR806/SA806
R
GND_IO
VDD_IO
10-BIT
SD
VIDEO
DATA
20-BIT
ED/HD
VIDEO
DATA
S_HSYNCP_HSYNC P_VSYNC P_BLANK S_VSYNC
11-BIT
DAC 1
DAC 1
11-BIT
DAC 2
DAC 2
11-BIT
DAC 3
DAC 3
11-BIT
DAC 4
DAC 4
11-BIT
DAC 5
DAC 5
11-BIT
DAC 6
DAC 6
MULTIPLEXER
REFERENCE
AND CABLE
DETECT
16x/4x OVERSAMPLING
DAC PLL
VIDEO TIMING GENERATOR
POWER
MANAGEMENT
CONTROL
CLKIN (2) PV
DD
PGND EXT_LF (2) V
REF
COMP (2)
R
SET
(2)
ED/HD INPUT
DEINTERLEAVE
PROGRAMMABLE
HDTV FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCbCr
HDTV
TEST
PATTERN
GENERATOR
YCbCr
TO
RGB MATRIX
G/B
RGB
ASYNC
BYPASS
RGB
DGND (2) V
DD
(2)
SCL/
MOSI
SDA/
SCLK
ALSB/
SPI_SS
SFL/
MISO
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
YUV
TO
YCrCb/
RGB
PROGRAMMABLE
CHROMINANCE
FILTER
ADD
BURST
RGB/YCrCb
TO
YUV
MATRIX
4:2:2 TO 4:4:4
HD DDR
DEINTERLEAVE
SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
4×
FILTER
AGND
V
AA
ADD
SYNC
VBI DATA SERVICE
INSERTION
PROGRAMMABLE
LUMINANCE
FILTER
ADV7342/ADV7343
64
GND_IO
63
CLKIN_B
62
S7
61
S6
60
S5
59
S4
58
S3
57
DGND
56
V
DD
55
S2
54
S1
53
S0
52
TEST5
51
TEST4
50
S_HSYNC
49
S_VSYNC
47
R
SET1
46
V
REF
45
COMP1
42
DAC 3
43
DAC 2
44
DAC 1
48
SFL/MISO
41
V
AA
40
AGND
39
DAC 4
37
DAC 6
36
R
SET2
35
COMP2
34
PV
DD
33
EXT_LF1
38
DAC 5
2
TEST0
3
TEST1
4
Y0
7
Y3
6
Y2
5
Y1
1
V
DD_IO
8
Y4
9
Y5
10
V
DD
12
Y6
13
Y7
14
TEST2
15
TEST3
16
C0
11
DGND
17
C1
18
C2
19
ALSB/SPI_SS
20
SDA/SCLK
21
SCL/MOSI
22 23
P_HSYNC
24
P_VSYNC
25
P_BLANK
26
C4 C3
27
C5
28
C6
29
C7
30
CLKIN_A
31 32
PGND
PIN 1
ADV7342
TOP VIEW
EXT_LF2
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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