Intel 21555 User Manual

21555 Non-Transparent PCI-to-
PCI Bridge
User Manual
July 2001
Order Number: 278321–002

Intel 21555 Specifications

General

Brand	Intel
Model	21555
Category	Network Hardware
Language	English

Summary

Introduction

Architectural Overview

Describes the buffers, registers, and control logic of the 21555.

Signal Descriptions

Primary PCI Bus Interface Signals

Describes the primary PCI bus interface signals, including address, data, command, and control lines.

Primary PCI Bus Interface 64-Bit Extension Signals

Details the primary PCI bus interface 64-bit extension signals.

Secondary PCI Bus Interface Signals

Describes the secondary PCI bus interface signals, including address, data, command, and control lines.

Secondary PCI Bus Interface 64-Bit Extension Signals

Details the secondary PCI bus interface 64-bit extension signals.

Address Decoding

CSR Address Decoding

Explains how Control and Status Registers (CSRs) are decoded.

Memory 0 Transaction Address Decoding

Describes address decoding for Memory 0 transactions.

I/O Transaction Address Decoding

Explains address decoding for I/O transactions.

Configuration Accesses

PCI Bus Transactions

Posted Write Transactions

Details memory write and MWI transactions forwarded by the 21555.

Delayed Write Transactions

Delayed Read Transactions

Initialization Requirements

Power Management, Hot-Swap, and Reset Signals

Details signals related to power management, hot-swap, and reset.

Reset Behavior

Describes the reset behavior of the 21555, including reset inputs and outputs.

21555 Initialization

Covers initialization and configuration mechanisms like SROM, local, and host processor.

Power Management Support

Explains the 21555's implementation of the PCI Power Management interface.

CompactPCI Hot-Swap Functionality

Clocking

Primary and Secondary PCI Bus Clock Signals

Describes the primary and secondary PCI bus clock signals.

Serial ROM Interface

SROM Interface Signals

SROMSROM Preload Operation

Details the SROM preload operation for configuration registers.

Arbitration

Primary PCI Bus Arbitration Signals

Secondary PCI Bus Arbitration Signals

Primary PCI Bus Arbitration

Explains the 21555's implementation of primary PCI bus arbitration.

Secondary PCI Bus Arbitration

Explains the 21555's implementation of secondary PCI bus arbitration.

Interrupt and Scratchpad Registers

Primary and Secondary PCI Bus Interrupt Signals

Interrupt Support

Details the 21555's interrupt request status and mask bits.

Error Handling

Error Signals

Parity Errors

System Error (SERR#) Reporting

List of Registers

Configuration Registers

Lists the configuration space address registers.

Control and Status Registers

Describes memory-mapped control and status registers.

Address Decoding

PCI Registers

Lists various PCI registers including command, status, and class code registers.

I2O Registers

Interrupt Registers