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21555
Intel 21555 User Manual
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21555 No
n-Transparent PC
I-to-PCI Bridg
e User Ma
nual
95
Serial RO
M Interf
ace
Figure 22
. SROM Eras
e Timing Diagram
Figure 23
. SROM Eras
e All Ope
ration
Figure 24
. SROM Chec
k St
atus Timing Diagram
A7479-01
A8
A0
111
pr_ad[1]
(sr_di)
sr_cs
pr_ad[0]
(sr_ck)
A7480-01
11
00
0
pr_ad[1]
(sr_di)
sr_cs
pr_ad[0]
(sr_ck)
A7481-01
pr_ad[2]
(sr_di)
sr_cs
pr_ad[0]
(sr_ck)
ready
busy
94
96
Table of Contents
Table of Contents
3
Preface
11
Cautions and Notes
12
Data Units
12
Numbering
12
Signal Nomenclature
13
Signal Type Abbreviations
13
Register Abbreviations
14
Introduction
15
Comparing a 21555 to a Transparent PPB
15
21555 Intelligent Controller Application
16
21555 And PPB Feature Comparison
17
Architectural Overview
18
Data Buffers
18
Registers
18
Control Logic
18
21555 Microarchitecture
19
Special Applications
20
Primary Bus VGA Support
20
Secondary Bus VGA Support
20
Programming Notes
20
Addressing
20
Decoded and Not Decoded Addresses
20
Transaction Forwarding
21
ROM Access
21
Signal Descriptions
23
Signal Pin Functional Groups
23
Primary PCI Bus Interface Signals
24
Primary PCI Bus Interface 64-Bit Extension Signals
26
Secondary PCI Bus Interface Signals
28
Secondary PCI Bus Interface 64-Bit Extension Signals
30
Miscellaneous Signals
31
Address Decoding
33
CSR Address Decoding
34
Expansion ROM Address Mapping (Decoding)
34
Memory 0 Transaction Address Decoding
34
Using the BAR Setup Registers
35
BAR Setup Register Example
35
Direct Address Translation
36
Address Format
36
Lookup Table Based Address Translation
37
Direct Offset Address Translation
37
Downstream Address Translation Example
37
Upstream Memory 2 Window Size
38
Address Translation Using a Lookup Table
39
Lookup Table Entry Format
40
Upstream Lookup Table Address Translation
40
Forwarding of 64-Bit Address Memory Transactions
41
Lookup Table Entry Format
41
I/O Transaction Address Decoding
42
Indirect I/O Transaction Generation
42
Dual-Address Transaction Forwarding
42
Subtractive Decoding of I/O Transactions
44
Configuration Accesses
44
Type 0 Accesses to 21555 Configuration Space
44
Initiation of Configuration Transactions by 21555
45
21555 Bar Summary
47
PCI Bus Transactions
49
Transactions Overview
49
Posted Write Transactions
50
Memory Write Transactions
51
Memory Write and Invalidate Transactions
51
64-Bit Extension Posted Write Transaction
52
Write Performance Tuning Options
52
Delayed Write Transactions
54
Delayed Read Transactions
55
Delayed Write Transaction Target Termination Returns
55
Nonprefetchable Reads
56
Delayed Read Transaction Target Termination Returns
56
Prefetchable Reads
57
Prefetchable Read Transactions Using the 64-Bit Extension
57
Read Performance Features and Tuning Options
57
Prefetch Boundaries
58
64-Bit and 32-Bit Transactions Initiated by the 21555
59
Target Terminations
60
Target Terminations Returned by the 21555
60
Transaction Termination Errors on the Target Bus
61
Ordering Rules
61
Transaction Ordering Rules
62
Initialization Requirements
65
Power Management, Hot-Swap, and Reset Signals
65
Reset Behavior
66
Reset Mechanisms
67
Central Function During Reset
68
21555 Initialization
68
With SROM, Local, and Host Processors
69
Without Serial Preload
69
Without Local Processor
70
Without Local Processor and Serial Preload
70
Without Host Processor
70
Power Management Support
70
Transitions between Power Management States
71
PME# Support
71
Power Management Actions
71
Power Management Data Register
72
Compactpci Hot-Swap Functionality
72
Overview of Compactpci Controller Hardware Interface
72
Insertion and Removal Process
73
Compactpci Hot-Swap Connections
73
21555 Hot-Swap Insertion and Removal
75
Clocking
77
Primary and Secondary PCI Bus Clock Signals
77
21555 Secondary Clock Outputs
78
Synchronous Secondary Clock Generation
78
66 Mhz Support
79
Parallel ROM Interface
81
Interface Signals
81
PROM Interface Signals
82
Parallel and Serial ROM Connection
84
PROM Read by CSR Access
84
Parallel and Serial ROM Connections
84
PROM Read Timing
85
PROM Write by CSR Access
86
PROM Dword Read
87
PROM Write Timing
87
Access Time and Strobe Control
88
Read and Write Strobe Timing
88
Attaching Additional Devices to the ROM Interface
89
Attaching Multiple Devices on the ROM Interface
90
Serial ROM Interface
91
SROM Interface Signals
91
SROMSROM Preload Operation
91
SROM Configuration Data Preload Format
92
SROM Operation by CSR Access
92
SROM Write All Timing Diagram
94
SROM Write Enable Timing Diagram
94
SROM Write Disable Timing Diagram
94
SROM Check Status Timing Diagram
95
SROM Erase Timing Diagram
95
SROM Erase All Operation
95
Arbitration
97
Primary PCI Bus Arbitration Signals
97
Secondary PCI Bus Arbitration Signals
97
Primary PCI Bus Arbitration
98
Secondary PCI Bus Arbitration
98
Secondary Bus Arbitration Using the Internal Arbiter
98
Secondary Arbiter Example
99
Secondary Bus Arbitration Using an External Arbiter
100
Arbiter Control Register
100
Interrupt and Scratchpad Registers
101
Primary and Secondary PCI Bus Interrupt Signals
101
Interrupt Support
101
Doorbell Interrupts
103
Scratchpad Registers
103
Error Handling
105
Error Signals
105
Primary PCI Bus Error Signals
105
Secondary PCI Bus Error Signals
106
Secondary PCI Bus Arbitration Signals
106
Parity Errors
107
Parity Error Responses
107
System Error (SERR#) Reporting
110
JTAG Test Port
111
JTAG Signals
111
Test Access Port Controller
112
Initialization
112
Signal Trst_L States
112
I2O Support
113
Inbound Message Passing
113
Outbound Message Passing
115
Notes
116
VPD Support
119
Reading VPD Information
119
Writing VPD Information
120
Register Cross Reference Table
121
Configuration Registers
122
List of Registers
121
Register Summary
121
Configuration Space Address Register
122
Control and Status Registers
126
CSR Address Map
126
Address Decoding
130
Primary and Secondary Address
130
Primary CSR and Downstream Memory 0 Bar
130
Secondary CSR Memory Bars
131
Primary and Secondary CSR I/O Bars
132
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR
133
Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR
134
Upper 32 Bits Downstream Memory 3 Bar
135
Upstream Memory 2 Bar
135
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register
136
Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base Register
137
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers
138
Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers
139
Configuration Transaction Generation Registers
140
Upper 32 Bits Downstream Memory 3 Setup Register
140
Downstream and Upstream Configuration Address Registers
141
Downstream Configuration Data and Upstream Configuration Data Registers
142
Configuration Own Bits Register
142
Configuration CSR
143
Downstream I/O Address and Upstream I/O Address Registers
144
Downstream I/O Data and Upstream I/O Data Registers
145
I/O Own Bits Registers
145
Lookup Table Offset Register
146
PCI Registers
147
Configuration Registers
147
Lookup Table Data Register
147
Upstream Memory 2 Lookup Table
147
Primary Interface Configuration Space Address Map
148
Secondary Interface Configuration Space Address Map
148
Vendor ID Register
148
Device ID Register
148
Primary and Secondary Command Registers
149
Primary and Secondary Status Registers
150
Revision ID (Rev ID) Register
151
Primary and Secondary Class Code Registers
152
Primary and Secondary Cache Line Size Registers
152
Primary Latency and Secondary Master Latency Timer Registers
153
Header Type Register
153
Bist Register
153
Subsystem Vendor ID Register
154
Subsystem ID Register
154
Enhanced Capabilities Pointer Register
154
Primary and Secondary Interrupt Line Registers
154
Primary and Secondary Interrupt Pin Registers
155
Primary and Secondary Minimum Grant Registers
155
Primary and Secondary Maximum Latency Registers
155
Device-Specific Control and Status Registers
156
Device-Specific Control and Status Address Map
156
Chip Control 0 Register
156
Chip Control 1 Register
160
Chip Status Register
162
Generic Own Bits Register
164
I2O Registers
165
I2O Outbound Post_List Status
165
I2O Outbound Post_List Interrupt Mask
165
I2O Inbound Post_List Status
165
I2O Inbound Post_List Interrupt Mask
166
I2O Inbound Queue
166
I2O Outbound Queue
166
I2O Inbound Free_List Head Pointer
167
I2O Inbound Post_List Tail Pointer
167
I2O Outbound Free_List Tail Pointer
167
I2O Outbound Post_List Head Pointer
167
I2O Inbound Post_List Counter
168
I2O Inbound Free_List Counter
168
I2O Outbound Post_List Counter
169
I2O Outbound Free_List Counter
169
Interrupt Registers
170
Chip Status CSR
170
Chip Set IRQ Mask Register
170
Chip Clear IRQ Mask Register
171
Upstream Page Boundary IRQ 0 Register
171
Upstream Page Boundary IRQ 1 Register
172
Upstream Page Boundary IRQ Mask 0 Register
172
Upstream Page Boundary IRQ Mask 1 Register
172
Primary Clear IRQ and Secondary Clear IRQ Registers
173
Primary Set IRQ and Secondary Set IRQ Registers
173
Scratchpad 0 through Scratchpad 7 Registers
174
Scratchpad Registers
174
PROM Registers
175
Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers
174
Primary Set IRQ Mask and Secondary Set IRQ Mask Registers
174
Primary Expansion ROM BAR
175
Primary Expansion ROM Setup Register
176
ROM Setup Register
177
ROM Data Register
177
ROM Address Register
178
ROM Control Register
178
SROM Registers
179
Mode Setting Configuration Register
179
Serial Preload Sequence
180
Arbiter Control
183
Error Registers
183
Primary SERR# Disable Register
184
Secondary SERR# Disable Register
184
Init Registers
185
Power Management ECP ID and Next Pointer Register
185
Power Management Capabilities Register
186
Power Management Control and Status Register
187
PMCSR Bridge Support Extensions
187
Power Management Data Register
188
JTAG Registers
190
Reset Control Register
188
JTAG Instruction Register Options
190
Bypass Register
191
Boundary-Scan Register
191
Boundary Scan Order
191
VPD Registers
192
Vital Product Data (VPD) ECP ID and Next Pointer Register
192
Vital Product Data (VPD) Address Register
193
VPD Data Register
193
Index
197
5
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Intel 21555 Specifications
General
Brand
Intel
Model
21555
Category
Network Hardware
Language
English
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