Intel 21555 User Manual

36 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Address Decoding
4.3.2 Direct Address Translation
With the exception of secondary bus transactions falling into the Upstream Memory 2 address
range (see Section 4.3.3) and all dual address transactions (Section 4.3.5), the 21555 uses direct address translation
when forwarding memory transactions from one interface to the other. Note that since transactions addressing the
bottom 4 KB of the Primary CSR and Downstream Memory 0 BAR are targeted at the 21555 CSRs, no forwarding
and therefore no address translation is performed. Direct address translation is used for transactions in that range
above the low 4 KB boundary.
A memory address may be thought of as a base address (as programmed in the Downstream and Upstream BARs)
with an offset from the base address, as shown in Figure 4.
When a memory transaction is forwarded downstream from the primary bus to the secondary bus, the primary bus
address can be mapped to another address in the secondary bus domain. The mapping is performed by substituting
a new base address for the base of the original address, as shown in Figure 5.
Figure 4. Address Format
A7462-01
Base Address
Address Map
Address
Offset
Base Offset

Intel 21555 Specifications

General

Brand	Intel
Model	21555
Category	Network Hardware
Language	English