21555 Non-Transparent PCI-to-PCI Bridge User Manual 33
Address Decoding 4
This chapter presents the theory of operation information about address mapping and decoding. See Chapter 16 for
specific information about addressing registers. The following areas are covered:
• Section 4.1, “CSR Address Decoding” on page 34.
• Section 4.2, “Expansion ROM Address Mapping (Decoding)” on page 34.
• Section 4.3, “Memory 0 Transaction Address Decoding” on page 34.
• Section 4.4, “I/O Transaction Address Decoding” on page 42.
• Section 4.5, “Configuration Accesses” on page 44.
The 21555 implements separate Base Address Registers (BARs) on both the primary and secondary interfaces. The
BARs denotes address ranges for downstream and upstream forwarding. This addressing is unlike the transparent
PCI-to-PCI Bridge (PPB), discussed in Chapter 2, which implements a flat address map encompassing both the
primary and secondary interfaces.
The 21555 BARs denote interface ranges for Control and Status Registers (CSR) access.
• Primary Interface – The 21555 responds to those transactions whose addresses fall into one of its primary BAR
ranges. All other I/O and memory transactions on the primary bus are ignored by the 21555. The address
ranges defined by the primary BARs reside in the primary, or system, address map.
• Secondary Interface – The 21555 responds to those transactions whose addresses reside in one of the
secondary BAR ranges. All other transactions on the secondary bus are ignored by the 21555. The address
ranges defined by the secondary BARs reside in the secondary, or local, address map.
The system and local address maps are independent of each other. The 21555 supports address translations between
the two address maps when forwarding transactions upstream or downstream.
Note: When enabled as a target, the 21555 ignores any transactions that it initiates as a master with the
exception of type 0 configuration transactions.
To Next Page
Loading...
Need help?
General