Intel 21555 - Page 102

102 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Interrupt and Scratchpad Registers
— Cleared by writing a 1 to the corresponding status bit in the Upstream Page Boundary IRQ 0 or 1 registers.
— Asserts s_inta_l when the corresponding mask bit is zero.
• A subsystem event is indicated by a rising edge on s_pme_l.
— Cleared by writing a 1 to the corresponding status bit in the Chip Status CSR.
— Asserts p_inta_l when the corresponding mask bit is zero.
• A power management transition from state D1 or D2 to state D0 occurs.
— Cleared by writing a 1 to the corresponding status bit in the Chip Status CSR.
— Asserts s_inta_l when the corresponding mask bit is zero.