Intel 21555 - Page 104

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Table of Contents3
Preface11
- Cautions and Notes12
- Data Units12
- Numbering12
- Signal Nomenclature13
- Signal Type Abbreviations13
- Register Abbreviations14
Introduction15
- Comparing a 21555 to a Transparent PPB15
- 21555 Intelligent Controller Application16
- 21555 And PPB Feature Comparison17
- Architectural Overview18
- 21555 Microarchitecture19
- Special Applications20
  - Primary Bus VGA Support20
  - Secondary Bus VGA Support20
- Programming Notes20
  - Addressing20
- Decoded and Not Decoded Addresses20
  - Transaction Forwarding21
  - ROM Access21
Signal Descriptions23
- Signal Pin Functional Groups23
- Primary PCI Bus Interface Signals24
- Primary PCI Bus Interface 64-Bit Extension Signals26
- Secondary PCI Bus Interface Signals28
- Secondary PCI Bus Interface 64-Bit Extension Signals30
- Miscellaneous Signals31
Address Decoding33
- CSR Address Decoding34
- Expansion ROM Address Mapping (Decoding)34
- Memory 0 Transaction Address Decoding34
  - Using the BAR Setup Registers35
- BAR Setup Register Example35
  - Direct Address Translation36
- Address Format36
  - Lookup Table Based Address Translation37
- Direct Offset Address Translation37
- Downstream Address Translation Example37
Upstream Memory 2 Window Size38
- Address Translation Using a Lookup Table39
  - Lookup Table Entry Format40
- Upstream Lookup Table Address Translation40
  - Forwarding of 64-Bit Address Memory Transactions41
- Lookup Table Entry Format41
- I/O Transaction Address Decoding42
  - Indirect I/O Transaction Generation42
- Dual-Address Transaction Forwarding42
  - Subtractive Decoding of I/O Transactions44
- Configuration Accesses44
  - Type 0 Accesses to 21555 Configuration Space44
  - Initiation of Configuration Transactions by 2155545
- 21555 Bar Summary47
PCI Bus Transactions49
- Transactions Overview49
- Posted Write Transactions50
- Delayed Write Transactions54
- Delayed Read Transactions55
Delayed Write Transaction Target Termination Returns55
- Nonprefetchable Reads56
Delayed Read Transaction Target Termination Returns56
- Prefetchable Reads57
- Prefetchable Read Transactions Using the 64-Bit Extension57
- Read Performance Features and Tuning Options57
Prefetch Boundaries58
- 64-Bit and 32-Bit Transactions Initiated by the 2155559
- Target Terminations60
  - Target Terminations Returned by the 2155560
  - Transaction Termination Errors on the Target Bus61
- Ordering Rules61
Transaction Ordering Rules62
Initialization Requirements65
- Power Management, Hot-Swap, and Reset Signals65
- Reset Behavior66
Reset Mechanisms67
- Central Function During Reset68
- 21555 Initialization68
- Power Management Support70
  - Transitions between Power Management States71
  - PME# Support71
Power Management Actions71
- Power Management Data Register72
- Compactpci Hot-Swap Functionality72
  - Overview of Compactpci Controller Hardware Interface72
  - Insertion and Removal Process73
- Compactpci Hot-Swap Connections73
- 21555 Hot-Swap Insertion and Removal75
Clocking77
- Primary and Secondary PCI Bus Clock Signals77
- 21555 Secondary Clock Outputs78
- Synchronous Secondary Clock Generation78
- 66 Mhz Support79
Parallel ROM Interface81
- Interface Signals81
PROM Interface Signals82
- Parallel and Serial ROM Connection84
- PROM Read by CSR Access84
- Parallel and Serial ROM Connections84
- PROM Read Timing85
- PROM Write by CSR Access86
- PROM Dword Read87
- PROM Write Timing87
- Access Time and Strobe Control88
- Read and Write Strobe Timing88
- Attaching Additional Devices to the ROM Interface89
- Attaching Multiple Devices on the ROM Interface90
Serial ROM Interface91
- SROM Interface Signals91
- SROMSROM Preload Operation91
- SROM Configuration Data Preload Format92
- SROM Operation by CSR Access92
- SROM Write All Timing Diagram94
- SROM Write Enable Timing Diagram94
- SROM Write Disable Timing Diagram94
- SROM Check Status Timing Diagram95
- SROM Erase Timing Diagram95
- SROM Erase All Operation95
Arbitration97
- Primary PCI Bus Arbitration Signals97
- Secondary PCI Bus Arbitration Signals97
- Primary PCI Bus Arbitration98
- Secondary PCI Bus Arbitration98
  - Secondary Bus Arbitration Using the Internal Arbiter98
- Secondary Arbiter Example99
  - Secondary Bus Arbitration Using an External Arbiter100
Arbiter Control Register100
Interrupt and Scratchpad Registers101
- Primary and Secondary PCI Bus Interrupt Signals101
- Interrupt Support101
- Doorbell Interrupts103
- Scratchpad Registers103
Error Handling105
- Error Signals105
- Parity Errors107
Parity Error Responses107
- System Error (SERR#) Reporting110
JTAG Test Port111
- JTAG Signals111
- Test Access Port Controller112
  - Initialization112
- Signal Trst_L States112
I2O Support113
- Inbound Message Passing113
- Outbound Message Passing115
- Notes116
VPD Support119
- Reading VPD Information119
- Writing VPD Information120
Register Cross Reference Table121
- Configuration Registers122
List of Registers121
- Register Summary121
Configuration Space Address Register122
- Control and Status Registers126
CSR Address Map126
- Address Decoding130
  - Primary and Secondary Address130
Primary CSR and Downstream Memory 0 Bar130
Secondary CSR Memory Bars131
Primary and Secondary CSR I/O Bars132
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR133
Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR134
Upper 32 Bits Downstream Memory 3 Bar135
Upstream Memory 2 Bar135
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Translated Base Register136
Downstream Memory 0, 2, 3, and Upstream Memory 1 Translated Base Register137
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 Setup Registers138
Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers139
- Configuration Transaction Generation Registers140
Upper 32 Bits Downstream Memory 3 Setup Register140
Downstream and Upstream Configuration Address Registers141
Downstream Configuration Data and Upstream Configuration Data Registers142
Configuration Own Bits Register142
Configuration CSR143
Downstream I/O Address and Upstream I/O Address Registers144
Downstream I/O Data and Upstream I/O Data Registers145
I/O Own Bits Registers145
Lookup Table Offset Register146
- PCI Registers147
  - Configuration Registers147
Lookup Table Data Register147
Upstream Memory 2 Lookup Table147
Primary Interface Configuration Space Address Map148
Secondary Interface Configuration Space Address Map148
Vendor ID Register148
Device ID Register148
- Primary and Secondary Command Registers149
Primary and Secondary Status Registers150
Revision ID (Rev ID) Register151
Primary and Secondary Class Code Registers152
Primary and Secondary Cache Line Size Registers152
Primary Latency and Secondary Master Latency Timer Registers153
Header Type Register153
Bist Register153
Subsystem Vendor ID Register154
Subsystem ID Register154
Enhanced Capabilities Pointer Register154
Primary and Secondary Interrupt Line Registers154
Primary and Secondary Interrupt Pin Registers155
Primary and Secondary Minimum Grant Registers155
Primary and Secondary Maximum Latency Registers155
- Device-Specific Control and Status Registers156
Device-Specific Control and Status Address Map156
Chip Control 0 Register156
Chip Control 1 Register160
Chip Status Register162
Generic Own Bits Register164
- I2O Registers165
I2O Outbound Post_List Status165
I2O Outbound Post_List Interrupt Mask165
I2O Inbound Post_List Status165
I2O Inbound Post_List Interrupt Mask166
I2O Inbound Queue166
I2O Outbound Queue166
I2O Inbound Free_List Head Pointer167
I2O Inbound Post_List Tail Pointer167
I2O Outbound Free_List Tail Pointer167
I2O Outbound Post_List Head Pointer167
I2O Inbound Post_List Counter168
I2O Inbound Free_List Counter168
I2O Outbound Post_List Counter169
I2O Outbound Free_List Counter169
- Interrupt Registers170
Chip Status CSR170
Chip Set IRQ Mask Register170
Chip Clear IRQ Mask Register171
Upstream Page Boundary IRQ 0 Register171
Upstream Page Boundary IRQ 1 Register172
Upstream Page Boundary IRQ Mask 0 Register172
Upstream Page Boundary IRQ Mask 1 Register172
Primary Clear IRQ and Secondary Clear IRQ Registers173
Primary Set IRQ and Secondary Set IRQ Registers173
- Scratchpad 0 through Scratchpad 7 Registers174
- Scratchpad Registers174
- PROM Registers175
Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers174
Primary Set IRQ Mask and Secondary Set IRQ Mask Registers174
Primary Expansion ROM BAR175
Primary Expansion ROM Setup Register176
ROM Setup Register177
ROM Data Register177
ROM Address Register178
ROM Control Register178
- SROM Registers179
Mode Setting Configuration Register179
Serial Preload Sequence180
- Arbiter Control183
- Error Registers183
Primary SERR# Disable Register184
Secondary SERR# Disable Register184
- Init Registers185
Power Management ECP ID and Next Pointer Register185
Power Management Capabilities Register186
Power Management Control and Status Register187
PMCSR Bridge Support Extensions187
- Power Management Data Register188
- JTAG Registers190
Reset Control Register188
JTAG Instruction Register Options190
Bypass Register191
Boundary-Scan Register191
Boundary Scan Order191
- VPD Registers192
Vital Product Data (VPD) ECP ID and Next Pointer Register192
Vital Product Data (VPD) Address Register193
VPD Data Register193
Index197

Intel 21555 - Page 104

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