21555 Non-Transparent PCI-to-PCI Bridge User Manual 27
Signal Descriptions
p_par64 TS
Primary PCI interface upper 32 bits parity.
The 21555 does not bus park this pin. This pin is tristated during the assertion of
p_rst_l. Signal p_par64 is driven to a valid value when the 64-bit extension is
disabled (p_req64_l is deasserted during p_rst_l assertion).
Signal p_par64 carries the even parity of the 36 bits of p_ad[63:32] and
p_cbe_l[7:4] for both address and data phases. Signal p_par64 is driven by the
initiator and is valid one clock cycle after the first address phase when a
dual-address command is used and p_req64_l is asserted. Signal p_par64 is also
valid one clock cycle after the second address phase of a dual-address transaction
when p_req64_l is asserted. Signal p_par64 is valid one clock cycle after valid data
is driven (indicated by assertion of p_irdy_l for write data and p_trdy_l for read
data), when both p_req64_l and p_ack64_l are asserted for that data phase. Signal
p_par64 is tristated by the device driving read or write data one clock cycle after the
p_ad lines are tristated.
Devices receiving data sample p_par64 as an input to check for possible parity
errors during 64-bit transactions.
When not driven, p_par64 is pulled up to a valid logic level through external
resistors.
p_req64_l STS
Primary PCI interface request 64-bit transfer.
Signal p_req64_l is sampled at secondary reset to enable the 64-bit extension on
the primary bus. When sampled low, the 64-bit extension is enabled.
Signal p_req64_l is asserted by the initiator to indicate that the initiator is requesting
64-bit data transfer. Signal p_req64_l has the same timing as p_frame_l. When
deasserting, p_req64_l is driven to a deasserted state for one clock cycle and is
then sustained by an external pull-up resistor.
The 21555 samples p_req64_l during primary bus reset to enable the 64-bit
extension signals. When p_req64_l is sampled high during reset, the primary 64-bit
extension is disabled and assumed not connected. The 21555 then drives
p_ad[63:32], p_cbe_l[7:4], and p_par64 to valid logic levels.
Table 7. Primary PCI Bus Interface 64-Bit Extension Signals (Sheet 2 of 2)
Signal Name Type Description
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