Intel 21555 - Page 4

4 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Contents
5.2 Posted Write Transactions..................................................................................................50
5.2.1 Memory Write Transactions...................................................................................51
5.2.2 Memory Write and Invalidate Transactions ...........................................................51
5.2.3 64-bit Extension Posted Write Transaction............................................................52
5.2.4 Write Performance Tuning Options .......................................................................52
5.3 Delayed Write Transactions................................................................................................54
5.4 Delayed Read Transactions ...............................................................................................55
5.4.1 Nonprefetchable Reads.........................................................................................56
5.4.2 Prefetchable Reads ...............................................................................................57
5.4.3 Prefetchable Read Transactions Using the 64-bit Extension ................................57
5.4.4 Read Performance Features and Tuning Options.................................................57
5.5 64-Bit and 32-Bit Transactions Initiated by the 21555........................................................59
5.6 Target Terminations............................................................................................................60
5.6.1 Target Terminations Returned by the 21555.........................................................60
5.6.2 Transaction Termination Errors on the Target Bus................................................61
5.7 Ordering Rules....................................................................................................................61
6 Initialization Requirements ............................................................................................................65
6.1 Power Management, Hot-Swap, and Reset Signals...........................................................65
6.2 Reset Behavior ...................................................................................................................66
6.2.1 Central Function During Reset ..............................................................................68
6.3 21555 Initialization..............................................................................................................68
6.3.1 With SROM, Local, and Host Processors..............................................................69
6.3.2 Without Serial Preload...........................................................................................69
6.3.3 Without Local Processor........................................................................................70
6.3.4 Without Local Processor and Serial Preload .........................................................70
6.3.5 Without Host Processor.........................................................................................70
6.4 Power Management Support..............................................................................................70
6.4.1 Transitions Between Power Management States..................................................71
6.4.2 PME# Support .......................................................................................................71
6.4.3 Power Management Data Register........................................................................72
6.5 CompactPCI Hot-Swap Functionality .................................................................................72
6.5.1 Overview of CompactPCI Controller Hardware Interface ......................................72
6.5.2 Insertion and Removal Process.............................................................................73
7 Clocking.........................................................................................................................................77
7.1 Primary and Secondary PCI Bus Clock Signals .................................................................77
7.2 21555 Secondary Clock Outputs........................................................................................78
7.3 66 MHz Support..................................................................................................................79
8 Parallel ROM Interface ..................................................................................................................81
8.1 Interface Signals.................................................................................................................81
8.2 Parallel and Serial ROM Connection..................................................................................84
8.3 PROM Read by CSR Access .............................................................................................84
8.4 PROM Write by CSR Access..............................................................................................86
8.5 PROM Dword Read............................................................................................................87
8.6 Access Time and Strobe Control........................................................................................88
8.7 Attaching Additional Devices to the ROM Interface............................................................89
9 Serial ROM Interface.....................................................................................................................91
9.1 SROM Interface Signals .....................................................................................................91