Intel 21555 User Manual

46 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Address Decoding
The 21555 provides a semaphore method that may be used to guarantee atomicity of the address and data register
accesses using the Upstream Configuration Own bit and Downstream Configuration Own bit. Atomicity of these
accesses is not guaranteed in hardware. When the corresponding Configuration Enable bit is not set, the Own bit is
treated as reserved. The following procedure should be used for downstream transactions:
1. The initiator of the transaction should read the Downstream Configuration Own bit for initiation of
transactions on the secondary bus. When the bit reads as zero, the initiator may proceed with the configuration
transaction sequence. When the bit reads as a one, the initiator should not proceed until a subsequent read of
the own bit returns a 0 (zero). The 21555 automatically sets the own bit to a 1 after it is read.
2. The initiator should write the target configuration address in the Downstream Configuration Address register.
3. The initiator should write or read the data in the Downstream Configuration Data register until a response other
than target retry is received.
4. Upon completion of the configuration transaction on the initiator bus, the 21555 automatically clears the
Downstream Configuration Own bit to a 0.
Upstream configuration transactions should use a similar process. To check the status of the own bits without read
side effects, read only copies of these bits are located in the Configuration CSR. Byte access of the Configuration
Own bits and their read-only copies should be used to avoid setting the Configuration Own bit for the opposite
interface.

Intel 21555 Specifications

General

Brand	Intel
Model	21555
Category	Network Hardware
Language	English