Intel 21555 User Manual

21555 Non-Transparent PCI-to-PCI Bridge User Manual 63
PCI Bus Transactions
Note: Performance may be affected if the Delayed Transaction Order Control bit is set, as the 21555
deasserts the PCI request signal between transactions. When the Delayed Transaction Order
Control bit is zero, the 21555 may keep REQ# asserted after a target retry or target disconnect if
another transaction is pending. See Table 77, “Chip Control 0 Register” on page 156.
Delayed completions are returned to the initiator when ready, regardless of the order in which corresponding
delayed requests were queued. A delayed read completion may not be returned to the initiator (the initiator receives
a target retry) when a posted write is ahead of the delayed completion in the queues. That is, the write was posted in
the direction of the completion, but before the read data was queued. In this case, the write must be delivered before
the read data can be returned to the initiator.

Intel 21555 Specifications

General

Brand	Intel
Model	21555
Category	Network Hardware
Language	English